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    CPU CONTROL METHOD, ELECTRONIC SYSTEM CONTROL METHOD AND ELECTRONIC SYSTEM
    11.
    发明申请
    CPU CONTROL METHOD, ELECTRONIC SYSTEM CONTROL METHOD AND ELECTRONIC SYSTEM 有权
    CPU控制方法，电子系统控制方法和电子系统

    公开(公告)号：US20160179747A1

    公开(公告)日：2016-06-23

    申请号：US14890427

    申请日：2015-04-24

    Applicant: MEDIATEK INC.

    Inventor： Chun-Hang Wei ,  Hung-Lin Chou ,  Nicholas Ching Hui Tang ,  Jia-Ming Chen ,  Ya-Ting Chang ,  Fan-Lei Liao

    IPC: G06F15/82 ,  G06F9/30

    CPC classification number: G06F15/82 ,  G06F9/30098 ,  G06F9/5055 ,  G06F9/5066

    Abstract: A CPU control method for controlling a first CPU and a second CPU The method comprises: (a) applying the first CPU to execute a first group of codes comprising at least one code if the first CPU is operating to perform a first function; and (c) applying the second CPU to execute a second group of codes comprising at least one code if the second CPU is operating to perform the first function. The first group of codes is optimized for the first CPU, the second group of codes is optimized for the second CPU and the first group of codes comprises at least one code different from the code for the second group of codes.

    Abstract translation: 一种用于控制第一CPU和第二CPU的CPU控制方法该方法包括：（a）如果第一CPU正在操作以执行第一功能，则应用第一CPU执行包括至少一个代码的第一组代码; 以及（c）如果所述第二CPU正在操作以执行所述第一功能，则应用所述第二CPU执行包括至少一个代码的第二组代码。 第一组代码针对第一个CPU进行了优化，第二组代码针对第二个CPU进行了优化，第一组代码包括与第二组代码不同的代码中的至少一个代码。

    TASK SCHEDULING METHOD FOR DISPATCHING TASKS BASED ON COMPUTING POWER OF DIFFERENT PROCESSOR CORES IN HETEROGENEOUS MULTI-CORE SYSTEM AND RELATED NON-TRANSITORY COMPUTER READABLE MEDIUM
    13.
    发明申请
    TASK SCHEDULING METHOD FOR DISPATCHING TASKS BASED ON COMPUTING POWER OF DIFFERENT PROCESSOR CORES IN HETEROGENEOUS MULTI-CORE SYSTEM AND RELATED NON-TRANSITORY COMPUTER READABLE MEDIUM 审中-公开
    基于异构多核系统中不同处理器的计算能力分配任务的任务调度方法和相关非终端计算机可读介质

    公开(公告)号：US20150121387A1

    公开(公告)日：2015-04-30

    申请号：US14480646

    申请日：2014-09-09

    Applicant: MEDIATEK INC.

    Inventor： Ya-Ting Chang ,  Jia-Ming Chen ,  Yu-Ming Lin ,  Yin Chen ,  Hung-Lin Chou ,  Yeh-Ji Chou ,  Shou-Wen Ho

    IPC: G06F9/48

    CPC classification number: G06F9/4881 ,  G06F2209/483 ,  G06F2209/501

    Abstract: A task scheduling method is applied to a heterogeneous multi-core system. The heterogeneous multi-core system has at least one first processor core and at least one second processor core. The task scheduling method includes: referring to task priorities of tasks of the heterogeneous processor cores to identify at least one first task of the tasks that belongs to a first priority task group, wherein each first task belonging to the first priority task group has a task priority not lower than task priorities of other tasks not belonging to the first priority task group; and dispatching at least one of the at least one first task to at least one run queue of at least one of the at least one first processor core.

    Abstract translation: 任务调度方法应用于异构多​​核系统。 异构多核系统具有至少一个第一处理器核和至少一个第二处理器核。 任务调度方法包括：参考异构处理器核的任务的任务优先级，以识别属于第一优先级任务组的任务的至少一个第一任务，其中属于第一优先级任务组的每个第一任务具有任务 优先级不低于不属于第一优先级任务组的其他任务的任务优先级; 以及将所述至少一个第一任务中的至少一个调度到所述至少一个第一处理器核心中的至少一个的至少一个运行队列。

    Multiprocessor systems having processors with different processing capabilities connecting to a clock generator
    14.
    发明授权
    Multiprocessor systems having processors with different processing capabilities connecting to a clock generator 有权

    公开(公告)号：US10551868B2

    公开(公告)日：2020-02-04

    申请号：US15440884

    申请日：2017-02-23

    Applicant: MediaTek Inc.

    Inventor： Hung-Lin Chou ,  Chih-Yung Chiu ,  Yu-Chung Chang ,  Chieh-Yuan Hsu

    IPC: G06F1/00 ,  G06F1/08 ,  G06F9/50

    Abstract: A multiprocessor system includes a first set of processors and a second set of processors. The first set of processors include a first set of standard cells and is configured to operate in a first frequency range. The second set of processors include a second set of standard cells and is configured to operate in a second frequency range. The first set of processors and the second set of processors have the same register-transfer level (RTL) description. Cells in the first set of standard cells have corresponding cells in the second set of standard cells with different characteristics. The first frequency range includes one or more frequencies higher than a maximum frequency in the second frequency range. The system also includes a clock generator that provides the same frequency to the first set of processors and the second set of processors.

    CLEARANCE MODE IN A MULTICORE PROCESSOR SYSTEM
    16.
    发明申请
    CLEARANCE MODE IN A MULTICORE PROCESSOR SYSTEM 审中-公开
    多处理器系统中的透明模式

    公开(公告)号：US20160314024A1

    公开(公告)日：2016-10-27

    申请号：US15098876

    申请日：2016-04-14

    Applicant: MediaTek Inc.

    Inventor： Ya-Ting Chang ,  Ming-Ju Wu ,  Pi-Cheng Chen ,  Jia-Ming Chen ,  Chung-Ho Chang ,  Pi-Cheng Hsiao ,  Hung-Lin Chou ,  Shih-Yen Chiu

    IPC: G06F9/50

    CPC classification number: G06F9/5088 ,  G06F1/3203 ,  G06F1/3287 ,  G06F1/329 ,  G06F9/5022 ,  G06F9/5094 ,  Y02D10/171 ,  Y02D10/22 ,  Y02D10/24 ,  Y02D50/20

    Abstract: A computing system supports a clearance mode for its processor cores. The computing system can transition a target processor core from an active mode into a clearance mode according to a system policy. The system policy determines the number of processor cores to be in the active mode. The transitioning into the clearance mode includes the operations of migrating work from the target processor core to one or more other processor cores in the active mode in the computing system; and removing the target processor core from a scheduling configuration of the computing system to prevent task assignment to the target processor core. When the target processor core is in the clearance mode, the target processor core is maintained in an online idle state in which the target processor core performs no work.

    Abstract translation: 计算系统支持其处理器核心的清除模式。 计算系统可以根据系统策略将目标处理器核心从活动模式转换到清除模式。 系统策略确定处于活动模式的处理器核心数。 过渡到清除模式包括在计算系统中将工作从目标处理器核心迁移到活动模式中的一个或多个其他处理器核心的操作; 以及从所述计算系统的调度配置中移除所述目标处理器核以防止对所述目标处理器核心的任务分配。 当目标处理器核心处于清除模式时，目标处理器核心维持在目标处理器核心不工作的在线空闲状态。

    Dynamic Adjustment Of Speed of Memory
    18.
    发明申请
    Dynamic Adjustment Of Speed of Memory 审中-公开
    内存速度的动态调整

    公开(公告)号：US20160110132A1

    公开(公告)日：2016-04-21

    申请号：US14967244

    申请日：2015-12-11

    Applicant: MediaTek Inc.

    Inventor： Chun-Hang Wei ,  Hung-Lin Chou ,  Nicholas Ching Hui Tang ,  Jia-Ming Chen

    IPC: G06F3/06

    CPC classification number: G06F13/1668 ,  Y02D10/14

    Abstract: A technique, as well as select implementations thereof, pertaining to dynamic adjustment of speed of memory is described. The technique may involve obtaining information indicative of memory transactions associated with a memory device from an external memory interface coupled to the memory device. The technique may also involve determining a runtime bandwidth of the memory device according to the memory transactions. The technique may further involve comparing the runtime bandwidth of the memory device to at least one threshold bandwidth. The technique may additionally involve adjusting the speed of the memory device according to a result of the comparing.

    Abstract translation: 描述了与存储器速度的动态调整有关的技术及其选择实现。 该技术可以涉及从耦合到存储器件的外部存储器接口获得指示与存储器件相关联的存储器事务的信息。 该技术还可以涉及根据存储器事务来确定存储器设备的运行时带宽。 该技术还可以包括将存储器件的运行时带宽与至少一个阈值带宽进行比较。 该技术可以另外包括根据比较的结果调整存储器件的速度。

    Heterogeneous Swap Space With Dynamic Thresholds
    19.
    发明申请
    Heterogeneous Swap Space With Dynamic Thresholds 审中-公开
    具有动态阈值的异构交换空间

    公开(公告)号：US20160098203A1

    公开(公告)日：2016-04-07

    申请号：US14965799

    申请日：2015-12-10

    Applicant: MediaTek Inc.

    Inventor： Chin-Wen Chang ,  Hung-Lin Chou ,  Nicholas Ching Hui Tang ,  Chih-Hsuan Tseng ,  Min-Hua Chen ,  Chung-Jung Lee

    IPC: G06F3/06

    CPC classification number: G06F12/08 ,  G06F2212/1016 ,  G06F2212/401

    Abstract: Techniques and implementations pertaining to a heterogeneous swap space with dynamic thresholds are provided. A technique may provide a list of a plurality of swap areas in a heterogeneous swap space. The swap areas may include at least two swap areas that are different from each other in one or more characteristics. The technique may also compute a dynamic threshold associated with a page in need of swapping and determine a priority level of the page in need of swapping based on the dynamic threshold. The technique may further select one of the swap areas from the list of swap areas for the swapping of the page in response to a determination of the priority level of the page.

    Abstract translation: 提供了具有动态阈值的异构交换空间的技术和实现。 技术可以提供异构交换空间中的多个交换区域的列表。 交换区域可以包括在一个或多个特征中彼此不同的至少两个交换区域。 该技术还可以计算与需要交换的页面相关联的动态阈值，并且基于动态阈值确定需要交换的页面的优先级。 该技术可以响应于页面的优先级的确定，从交换区域列表中进一步选择交换区域中的一个，以交换页面。

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