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1.发明申请METHOD AND APPARATUS FOR CONTROLLING DATA MIGRATION IN MULTI-CHANNEL MEMORY DEVICE 有权用于控制多通道存储器件中的数据移动的方法和装置公开(公告)号：US20160342343A1
公开(公告)日：2016-11-24
申请号：US14736261
申请日：2015-06-10
Applicant: MEDIATEK INC.
Inventor： Hsueh-Bing Yen
IPC: G06F3/06
Abstract: A memory system has a memory device and a data migration control circuit. The memory device has a plurality of memory spaces accessed via a plurality of memory channels, respectively. The data migration control circuit controls a first stored data in a second memory space to migrate to a first memory space. When a first data piece of the first stored data is requested during data migration of the first data piece, the data migration control circuit blocks data access of the first data piece until the first data piece is fully stored into the first memory space, where a size of the first data piece is smaller than a size of the first stored data.
Abstract translation: 存储器系统具有存储器件和数据迁移控制电路。 存储器件具有分别通过多个存储器通道访问的多个存储器空间。 数据迁移控制电路控制第二存储器空间中的第一存储数据以迁移到第一存储器空间。 当在第一数据段的数据迁移期间请求第一存储数据的第一数据段时，数据迁移控制电路阻止第一数据段的数据访问，直到第一数据段被完全存储到第一存储器空间中，其中 第一数据段的大小小于第一存储数据的大小。
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公开(公告)号：US20180267890A1
公开(公告)日：2018-09-20
申请号：US15983090
申请日：2018-05-18
Applicant: MediaTek Inc.
Inventor： Hsueh-Bing Yen
Abstract: A memory system has a memory device and a data migration control circuit. The memory device has a plurality of memory spaces accessed via a plurality of memory channels, respectively. The data migration control circuit controls a first stored data in a second memory space to migrate to a first memory space. When a first data piece of the first stored data is requested during data migration of the first data piece, the data migration control circuit blocks data access of the first data piece until the first data piece is fully stored into the first memory space, where a size of the first data piece is smaller than a size of the first stored data.
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3.发明授权公开(公告)号：US10001856B2
公开(公告)日：2018-06-19
申请号：US15133193
申请日：2016-04-19
Applicant: MediaTek Inc.
Inventor： Po-Hua Huang , Hsueh-Bing Yen , Chiung-Fu Chen
CPC classification number: G06F3/0412 , G06F1/206 , G06F1/3206 , G06F1/3262 , G06F1/3265 , G09G5/18 , G09G2310/08 , Y02D10/153
Abstract: Techniques pertaining to dynamic enablement, disablement and adjustment of offset of a virtual periodic timing control signal based on one or more predefined events are described. A method may determine whether a first predefined event is beginning. The method may also enable an offset of the virtual periodic timing control signal for synchronizing one or more first system modules in response to a determination that the first predefined event is beginning. The one or more first system modules may be configured to control one or more operations of one or more second system modules. The one or more second system modules may be configured to process one or more image frames. The method may further determine whether the first predefined event is ending. The method may additionally disable the offset in response to a determination that the first predefined event is ending.
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Patent Agency Ranking
4.发明申请Dynamic Enablement, Disablement And Adjustment Of Offset Of A Periodic Timing Control Signal 有权周期性定时控制信号偏移的动态启用，禁用和调整公开(公告)号：US20160231863A1
公开(公告)日：2016-08-11
申请号：US15133193
申请日：2016-04-19
Applicant: MediaTek Inc.
Inventor： Po-Hua Huang , Hsueh-Bing Yen , Chiung-Fu Chen
CPC classification number: G06F3/0412 , G06F1/206 , G06F1/3206 , G06F1/3262 , G06F1/3265 , G09G5/18 , G09G2310/08 , Y02D10/153
Abstract: Techniques pertaining to dynamic enablement, disablement and adjustment of offset of a virtual periodic timing control signal based on one or more predefined events are described. A method may determine whether a first predefined event is beginning. The method may also enable an offset of the virtual periodic timing control signal for synchronizing one or more first system modules in response to a determination that the first predefined event is beginning. The one or more first system modules may be configured to control one or more operations of one or more second system modules. The one or more second system modules may be configured to process one or more image frames. The method may further determine whether the first predefined event is ending. The method may additionally disable the offset in response to a determination that the first predefined event is ending.
Abstract translation: 描述了关于基于一个或多个预定义事件的虚拟周期性定时控制信号的偏移的动态启用，禁用和调整的技术。 方法可以确定第一预定义事件是否开始。 响应于第一预定义事件开始的确定，该方法还可以实现虚拟周期性定时控制信号的偏移，用于同步一个或多个第一系统模块。 一个或多个第一系统模块可以被配置为控制一个或多个第二系统模块的一个或多个操作。 一个或多个第二系统模块可以被配置为处理一个或多个图像帧。 该方法还可以确定第一预定义事件是否正在结束。 响应于第一预定义事件结束的确定，该方法还可以禁用偏移。
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公开(公告)号：US09122616B2
公开(公告)日：2015-09-01
申请号：US14464712
申请日：2014-08-21
Applicant: MEDIATEK INC.
Inventor： You-Ming Tsao , Hsueh-Bing Yen
CPC classification number: G06F12/0893 , G06F12/0806 , G06F12/0848 , G06F13/16 , G06F13/1652 , G06F2212/306 , G06F2212/601
Abstract: A method for performing dynamic configuration includes: freezing a bus between a portion of a dynamic configurable cache and at least one of a plurality of cores/processors by pending a request from the at least one of the cores/processors to the portion of the dynamic configurable cache during a bus freeze period, wherein the plurality of cores/processors are allowed to access the dynamic configurable cache and the at least one of the plurality of cores/processors is allowed to access the portion of the dynamic configurable cache; and adjusting a size of the portion of the dynamic configurable cache, wherein the portion of the dynamic configurable cache is capable of caching/storing information for the at least one of the plurality of cores/processors. An associated apparatus is also provided. In particular, the apparatus includes the plurality of cores/processors, the dynamic configurable cache, and a dynamic configurable cache controller, and can operate according to the method.
Abstract translation: 用于执行动态配置的方法包括：通过暂停从至少一个核/处理器到动态的部分的请求来将动态可配置高速缓存的一部分与多个核/处理器中的至少一个之间的总线冻结 在总线冻结期间可配置缓存，其中所述多个核心/处理器被允许访问所述动态可配置高速缓存，并且所述多个核心/处理器中的所述至少一个核/处理器被允许访问所述动态可配置高速缓存的所述部分; 以及调整所述动态可配置高速缓存的所述部分的大小，其中所述动态可配置高速缓存的所述部分能够高速缓存/存储所述多个核心/处理器中的所述至少一个核心/处理器的信息。 还提供了一种相关联的装置。 特别地，该装置包括多个核心/处理器，动态可配置高速缓存和动态可配置高速缓存控制器，并且可以根据该方法进行操作。
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公开(公告)号：US10002072B2
公开(公告)日：2018-06-19
申请号：US14736261
申请日：2015-06-10
Applicant: MEDIATEK INC.
Inventor： Hsueh-Bing Yen
Abstract: A memory system has a memory device and a data migration control circuit. The memory device has a plurality of memory spaces accessed via a plurality of memory channels, respectively. The data migration control circuit controls a first stored data in a second memory space to migrate to a first memory space. When a first data piece of the first stored data is requested during data migration of the first data piece, the data migration control circuit blocks data access of the first data piece until the first data piece is fully stored into the first memory space, where a size of the first data piece is smaller than a size of the first stored data.
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7.发明申请METHOD FOR CONTROLLING MEMORY DEVICE TO ACHIEVE MORE POWER SAVING AND RELATED APPARATUS THEREOF 审中-公开用于控制存储器件以实现更多省电的方法及其相关装置公开(公告)号：US20160062691A1
公开(公告)日：2016-03-03
申请号：US14784037
申请日：2015-03-13
Applicant: MEDIATEK INC.
Inventor： Chin-Wen Chang , Hsueh-Bing Yen , Hung-Lin Chou , Kuo-Hsien Lu , Kuang-Ting Chien , Chih-Chieh Liu , Nicholas Ching Hui Tang
CPC classification number: G06F3/0625 , G06F1/3296 , G06F3/0644 , G06F3/0673 , G11C11/40615 , G11C11/40622 , G11C11/4072 , G11C2207/2227 , G11C2211/4067
Abstract: A memory management method includes: performing a first-level collection operation upon first storage units in a memory pool allocated in a memory device; and after the first storage units are processed by the first-level collection operation, performing a second-level collection operation upon second storage units in the memory pool allocated in the memory device, wherein one of the first-level collection operation and the second-level collection operation is a page-level collection operation, and another of the first-level collection operation and the second-level collection operation is a bank-level collection operation.
Abstract translation: 存储器管理方法包括：对分配在存储器件中的存储器池中的第一存储单元执行第一级收集操作; 并且在通过第一级收集操作处理第一存储单元之后，在分配在存储器件中的存储器池中的第二存储单元上执行二级收集操作，其中第一级收集操作和第二级收集操作之一， 级别收集操作是页级收集操作，而第一级收集操作和第二级收集操作中的另一种是银行级收集操作。
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公开(公告)号：US20140365730A1
公开(公告)日：2014-12-11
申请号：US14464712
申请日：2014-08-21
Applicant: MEDIATEK INC.
Inventor： You-Ming Tsao , Hsueh-Bing Yen
CPC classification number: G06F12/0893 , G06F12/0806 , G06F12/0848 , G06F13/16 , G06F13/1652 , G06F2212/306 , G06F2212/601
Abstract: A method for performing dynamic configuration includes: freezing a bus between a portion of a dynamic configurable cache and at least one of a plurality of cores/processors by pending a request from the at least one of the cores/processors to the portion of the dynamic configurable cache during a bus freeze period, wherein the plurality of cores/processors are allowed to access the dynamic configurable cache and the at least one of the plurality of cores/processors is allowed to access the portion of the dynamic configurable cache; and adjusting a size of the portion of the dynamic configurable cache, wherein the portion of the dynamic configurable cache is capable of caching/storing information for the at least one of the plurality of cores/processors. An associated apparatus is also provided. In particular, the apparatus includes the plurality of cores/processors, the dynamic configurable cache, and a dynamic configurable cache controller, and can operate according to the method.
Abstract translation: 用于执行动态配置的方法包括：通过暂停从至少一个核/处理器到动态的部分的请求来将动态可配置高速缓存的一部分与多个核/处理器中的至少一个之间的总线冻结 在总线冻结期间可配置缓存，其中所述多个核心/处理器被允许访问所述动态可配置高速缓存，并且所述多个核心/处理器中的所述至少一个核/处理器被允许访问所述动态可配置高速缓存的所述部分; 以及调整所述动态可配置高速缓存的所述部分的大小，其中所述动态可配置高速缓存的所述部分能够高速缓存/存储所述多个核心/处理器中的所述至少一个核心/处理器的信息。 还提供了一种相关联的装置。 特别地，该装置包括多个核心/处理器，动态可配置高速缓存和动态可配置高速缓存控制器，并且可以根据该方法进行操作。
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