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    Snapshot data and hibernation data processing methods and devices
    2.
    发明授权
    Snapshot data and hibernation data processing methods and devices 有权

    公开(公告)号：US10108820B2

    公开(公告)日：2018-10-23

    申请号：US14812243

    申请日：2015-07-29

    Applicant: MediaTek Inc.

    Inventor： Wen-Long Yang ,  Jia-Ming Chen ,  Ming-Yueh Chuang ,  Nicholas Ching Hui Tang ,  Yu-Ming Lin

    IPC: G06F12/14 ,  G06F21/78 ,  G06F17/30 ,  G06F12/08

    Abstract: A method for operating an electronic device, and an electronic device, are provided. In the normal operation state of the electronic device, data which is stored in the main storage device of the electronic device is encrypted by a first encryption algorithm prior to being stored in a non-volatile storage device of the electronic device. The method includes the steps of generating snapshot data in the main storage device when the electronic device is entering a hibernation state, allocating space in the non-volatile storage device for storing the snapshot data, and storing the snapshot data in the space without encrypting the snapshot data using the first encryption algorithm.

    Multi-core processor systems and methods for assigning tasks in a multi-core processor system
    4.
    发明授权
    Multi-core processor systems and methods for assigning tasks in a multi-core processor system 有权

    公开(公告)号：US09852005B2

    公开(公告)日：2017-12-26

    申请号：US14799921

    申请日：2015-07-15

    Applicant: MediaTek Inc.

    Inventor： Ya-Ting Chang ,  Yu-Ting Chen ,  Yu-Ming Lin ,  Jia-Ming Chen ,  Hung-Lin Chou ,  Tzu-Jen Lo

    IPC: G06F9/48

    CPC classification number: G06F9/4881 ,  G06F2209/483

    Abstract: A multi-core processor system and a method for assigning tasks are provided. The multi-core processor system includes a plurality of processor cores, configured to perform a plurality of tasks, and each of the tasks is in a respective one of a plurality of scheduling classes. The multi-core processor system further includes a task scheduler, configured to obtain first task assignment information about tasks in a first scheduling class assigned to the processor cores, obtain second task assignment information about tasks in one or more other scheduling classes assigned to the processor cores, and refer to the first task assignment information and the second task assignment information to assign a runnable task in the first scheduling class to one of the processor cores.

    DYNAMIC SWITCHING OF VOLTAGE REGULATORS IN A MULTIPROCESSOR SYSTEM
    5.
    发明申请
    DYNAMIC SWITCHING OF VOLTAGE REGULATORS IN A MULTIPROCESSOR SYSTEM 审中-公开
    电力调节器在多处理器系统中的动态切换

    公开(公告)号：US20170023997A1

    公开(公告)日：2017-01-26

    申请号：US15071780

    申请日：2016-03-16

    Applicant: MediaTek Inc.

    Inventor： Jia-Ming Chen ,  Hung-Lin Chou ,  Pi-Cheng Hsiao ,  Yen-Lin Lee ,  Ya-Ting Chang ,  Jih-Ming Hsu

    IPC: G06F1/32 ,  G06F9/50 ,  G06F1/26

    CPC classification number: G06F1/3234 ,  G06F1/263 ,  G06F1/3206 ,  G06F1/3287 ,  G06F9/5094 ,  Y02D10/171

    Abstract: A switch interconnect is dynamically controlled at runtime to connect power sources to processing units in a multiprocessor system. Each power source is shareable by the processing units and each processing unit has a required voltage for processing a workload. When a system condition is detected at runtime, the switch interconnect is controlled to change a connection between at least one processing unit and a shared power source to maximize power efficiency. The shared power source is one of the power sources that supports multiple processing units having different required voltages.

    Abstract translation: 交换机互连在运行时动态控制，以将电源连接到多处理器系统中的处理单元。 每个电源可由处理单元共享，并且每个处理单元具有用于处理工作负载的所需电压。 当在运行时检测到系统条件时，控制开关互连以改变至少一个处理单元和共享电源之间的连接以最大化功率效率。 共享电源是支持具有不同所需电压的多个处理单元的电源之一。

    Dynamic cache resource allocation for quality of service and system power reduction
    6.
    发明授权
    Dynamic cache resource allocation for quality of service and system power reduction 有权

    公开(公告)号：US12204450B2

    公开(公告)日：2025-01-21

    申请号：US18451698

    申请日：2023-08-17

    Applicant: MediaTek Inc.

    Inventor： Yu-Pin Chen ,  Jia-Ming Chen ,  Chien-Yuan Lai ,  Ya Ting Chang ,  Cheng-Tse Chen

    IPC: G06F12/0811 ,  G06F12/084

    Abstract: A computing system performs shared cache allocation to allocate cache resources to groups of tasks. The computing system monitors the bandwidth at a memory hierarchy device that is at a next level to the cache in a memory hierarchy of the computing system. The computing system estimates a change in dynamic power from a corresponding change in the bandwidth before and after the cache resources are allocated. The allocation of the cache resources are adjusted according to an allocation policy that receives inputs including the estimated change in the dynamic power and a performance indication of task execution.

    Apparatus and method for controlling multi-core processor of computing system
    7.
    发明授权
    Apparatus and method for controlling multi-core processor of computing system 有权

    公开(公告)号：US10031574B2

    公开(公告)日：2018-07-24

    申请号：US14845879

    申请日：2015-09-04

    Applicant: MediaTek Inc.

    Inventor： Jih-Ming Hsu ,  Yen-Lin Lee ,  Jia-Ming Chen ,  Shih-Yen Chiu ,  Chung-Ho Chang ,  Ya-Ting Chang ,  Ming-Hsien Lee

    IPC: G06F1/32

    Abstract: A computing system includes a multi-core processor and a core controller. The core controller is for: monitoring utilization of the multi-core processor; calculating a target performance index according to the utilization of the multi-core processor, a target utilization and a first performance index, wherein the first performance index is associated with a first entry of a dynamic voltage frequency scaling (DVFS) table that corresponds to a current setting for the multi-core processor; and selecting a second entry of the DVFS table that corresponds to a target-setting according to the target performance index and a second performance index that is associated with the second entry. The target-setting is used to configure the multi-core processor.

    CLEARANCE MODE IN A MULTICORE PROCESSOR SYSTEM
    9.
    发明申请
    CLEARANCE MODE IN A MULTICORE PROCESSOR SYSTEM 审中-公开
    多处理器系统中的透明模式

    公开(公告)号：US20160314024A1

    公开(公告)日：2016-10-27

    申请号：US15098876

    申请日：2016-04-14

    Applicant: MediaTek Inc.

    Inventor： Ya-Ting Chang ,  Ming-Ju Wu ,  Pi-Cheng Chen ,  Jia-Ming Chen ,  Chung-Ho Chang ,  Pi-Cheng Hsiao ,  Hung-Lin Chou ,  Shih-Yen Chiu

    IPC: G06F9/50

    CPC classification number: G06F9/5088 ,  G06F1/3203 ,  G06F1/3287 ,  G06F1/329 ,  G06F9/5022 ,  G06F9/5094 ,  Y02D10/171 ,  Y02D10/22 ,  Y02D10/24 ,  Y02D50/20

    Abstract: A computing system supports a clearance mode for its processor cores. The computing system can transition a target processor core from an active mode into a clearance mode according to a system policy. The system policy determines the number of processor cores to be in the active mode. The transitioning into the clearance mode includes the operations of migrating work from the target processor core to one or more other processor cores in the active mode in the computing system; and removing the target processor core from a scheduling configuration of the computing system to prevent task assignment to the target processor core. When the target processor core is in the clearance mode, the target processor core is maintained in an online idle state in which the target processor core performs no work.

    Abstract translation: 计算系统支持其处理器核心的清除模式。 计算系统可以根据系统策略将目标处理器核心从活动模式转换到清除模式。 系统策略确定处于活动模式的处理器核心数。 过渡到清除模式包括在计算系统中将工作从目标处理器核心迁移到活动模式中的一个或多个其他处理器核心的操作; 以及从所述计算系统的调度配置中移除所述目标处理器核以防止对所述目标处理器核心的任务分配。 当目标处理器核心处于清除模式时，目标处理器核心维持在目标处理器核心不工作的在线空闲状态。

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