公开(公告)号：US20230169317A1

公开(公告)日：2023-06-01

申请号：US18059861

申请日：2022-11-29

Applicant: SK hynix Inc. ,  Korea Advanced Institute of Science and Technology (KAIST)

Inventor： Yang-Kyu CHOI ,  Joon-Kyu HAN

IPC: G06N3/063 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L29/66

CPC classification number: G06N3/063 ,  H01L27/11526 ,  H01L27/11573 ,  H01L29/792 ,  H01L29/6684 ,  H01L29/7839 ,  H01L29/7883 ,  H01L29/66825

Abstract: A neuromorphic devices may be formed having a three-dimensional stacked structure. The neuromorphic device may include a lower device formed on a substrate, an interlayer insulating layer formed on the substrate to cover the lower device, a synapse device having a Schottky barrier transistor structure formed on the interlayer insulating layer, and a vertical connection wiring formed in the interlayer insulating layer to electrically connect the lower device and the synapse device. The synapse device may include a channel, a source having a metal silicide forming a first Schottky junction with the channel, a drain having a metal silicide forming a second Schottky junction with the channel, a floating gate for a synaptic operation, and a control gate. The synapse device may be formed using only low-temperature processes performed at less than about 500° C.

公开(公告)号：US20220012576A1

公开(公告)日：2022-01-13

申请号：US17371364

申请日：2021-07-09

Applicant: Korea Advanced Institute Of Science And Technology

Inventor： Yang-Kyu CHOI ,  Joon-Kyu HAN ,  Geon-Beom LEE ,  Jinki KIM

IPC: G06N3/063 ,  H01L29/872

Abstract: A neuromorphic synaptic device based on a charge trap and having linearity and symmetricity improved by using a schottky junction and a neuromorphic system using the same are provided. The neuromorphic synaptic device includes a body layer formed on a semiconductor substrate, a source and a drain formed at a left side and a right side, or an upper side and a lower side of the body layer, a contact metal to form a schottky junction by making contact with the source and the drain, a gate insulating layer formed on the body layer, and including an oxide layer and a charge storage layer, and a gate formed on the gate insulating layer.

公开(公告)号：US20170194428A1

公开(公告)日：2017-07-06

申请号：US15041559

申请日：2016-02-11

Applicant: Korea Advanced Institute of Science And Technology

Inventor： Yang-Kyu CHOI ,  Jun-Young PARK

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/266 ,  H01L29/66 ,  H01L21/308

CPC classification number: H01L29/0673 ,  H01L21/02694 ,  H01L21/266 ,  H01L21/30604 ,  H01L21/3081 ,  H01L29/42392 ,  H01L29/66356 ,  H01L29/66568 ,  H01L29/7391

Abstract: A tunneling field-effect transistor may be provided that includes: a substrate; a source which is formed on the substrate and into which p+ type impurity ion is injected; a drain which is formed on the substrate and into which n+ type impurity ion is injected; a plurality of vertically stacked nanowire channels which are formed on the substrate; a gate insulation layer which is formed on the plurality of nanowire channels; and a gate which is formed on the gate insulation layer. As a result, it is possible to generate a higher driving current without changing the length of the gate and the area of the channel (degree of integration).

公开(公告)号：US20170162579A1

公开(公告)日：2017-06-08

申请号：US15044702

申请日：2016-02-16

Applicant: Korea Advanced Institute of Science And Technology

Inventor： Yang-Kyu CHOI ,  Jun-Young PARK ,  Byung-Hyun LEE ,  Dae-Chul AHN

IPC: H01L27/108 ,  H01L29/165 ,  H01L29/16 ,  H01L29/161 ,  G11C7/10 ,  H01L21/308 ,  H01L21/02 ,  H01L29/423 ,  G11C11/409 ,  H01L29/06 ,  H01L21/265

CPC classification number: H01L27/10802 ,  G11C7/1072 ,  G11C11/404 ,  G11C11/409 ,  G11C11/565 ,  G11C2211/4016 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/3081 ,  H01L21/3083 ,  H01L29/0673 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/66439

Abstract: A multi-bit capacitorless DRAM according to the embodiment of the present invention may be provided that includes: a substrate; a source and a drain formed on the substrate; a plurality of nanowire channels formed on the substrate; a gate insulation layer formed in the plurality of nanowire channels; and a gate formed on the gate insulation layer. Two or more nanowire channels among the plurality of nanowire channels have different threshold voltages. Each of the nanowire channels includes: a silicon layer; a first epitaxial layer which is formed to surround the silicon layer; and a second epitaxial layer which is formed to surround the first epitaxial layer. As a result, the high integration multi-bit capacitorless DRAM which operates at multi-bits can be implemented and a performance of accumulating excess holes can be improved by using energy band gap.

公开(公告)号：US20160314319A1

公开(公告)日：2016-10-27

申请号：US15007630

申请日：2016-01-27

Applicant: Korea Advanced Institute of Science And Technology

Inventor： Yang-Kyu CHOI ,  Jun-Young PARK ,  Dong-II MOON

IPC: G06F21/81 ,  G06F21/55 ,  H04L29/06

Abstract: Disclosed are a hardware-based selective security apparatus and a security method using the same. The security apparatus according to an embodiment of the present invention includes: a transistor including a source electrode, a drain electrode, and a gate electrode composed of at least two electrodes; and a controller which selectively sets a security level 1 or a security level 2 by controlling a magnitude of a voltage which is applied to the gate electrode. According to the present invention, since there is no necessity of an additional space for a separate chip required by an existing hardware based security method, it is possible to obtain a recoverable hardware based security method which uses spaces usefully and has economic efficiency. Also, a recoverable security level and an irrecoverable security level are selectively applied, so that it is possible to implement an enhanced hardware-based security method.

Abstract translation: 公开了一种基于硬件的选择性安全装置和使用其的安全方法。 根据本发明实施例的安全装置包括：晶体管，包括源电极，漏电极和由至少两个电极组成的栅电极; 以及控制器，其通过控制施加到栅电极的电压的大小来选择性地设置安全级别1或安全级别2。 根据本发明，由于不需要通过现有的基于硬件的安全方法所需的单独的芯片的额外空间，因此可以获得可有效利用空间并具有经济效率的可恢复的基于硬件的安全方法。 此外，可选择地应用可恢复的安全级别和不可恢复的安全级别，使得可以实现增强的基于硬件的安全方法。