公开(公告)号：US20170162579A1

公开(公告)日：2017-06-08

申请号：US15044702

申请日：2016-02-16

Applicant: Korea Advanced Institute of Science And Technology

Inventor： Yang-Kyu CHOI ,  Jun-Young PARK ,  Byung-Hyun LEE ,  Dae-Chul AHN

IPC: H01L27/108 ,  H01L29/165 ,  H01L29/16 ,  H01L29/161 ,  G11C7/10 ,  H01L21/308 ,  H01L21/02 ,  H01L29/423 ,  G11C11/409 ,  H01L29/06 ,  H01L21/265

CPC classification number: H01L27/10802 ,  G11C7/1072 ,  G11C11/404 ,  G11C11/409 ,  G11C11/565 ,  G11C2211/4016 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/3081 ,  H01L21/3083 ,  H01L29/0673 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/66439

Abstract: A multi-bit capacitorless DRAM according to the embodiment of the present invention may be provided that includes: a substrate; a source and a drain formed on the substrate; a plurality of nanowire channels formed on the substrate; a gate insulation layer formed in the plurality of nanowire channels; and a gate formed on the gate insulation layer. Two or more nanowire channels among the plurality of nanowire channels have different threshold voltages. Each of the nanowire channels includes: a silicon layer; a first epitaxial layer which is formed to surround the silicon layer; and a second epitaxial layer which is formed to surround the first epitaxial layer. As a result, the high integration multi-bit capacitorless DRAM which operates at multi-bits can be implemented and a performance of accumulating excess holes can be improved by using energy band gap.