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    Latch-up prevention for memory cells
    12.
    发明申请
    Latch-up prevention for memory cells 审中-公开
    记忆细胞的锁定预防

    公开(公告)号：US20060128090A1

    公开(公告)日：2006-06-15

    申请号：US11353180

    申请日：2006-02-13

    Applicant: John Porter ,  William Thompson

    Inventor： John Porter ,  William Thompson

    IPC: H01L21/8238

    CPC classification number: H01L27/11 ,  G11C11/412 ,  H01L27/1104

    Abstract: A method of fabricating a memory cell and corresponding memory cell structure are provided. According to the method, a pull-up transistor and a pull-down transistor are formed in a semiconductor structure of the memory cell. The pull-up transistor is coupled to the pull down transistor. The pull-up transistor is coupled to a contact within said semiconductor structure such that the pull-up transistor is coupled to a voltage input through parasitic resistance of the semiconductor structure. Additional embodiments are disclosed.

    Abstract translation: 提供了一种制造存储单元和相应的存储单元结构的方法。 根据该方法，在存储单元的半导体结构中形成上拉晶体管和下拉晶体管。 上拉晶体管耦合到下拉晶体管。 上拉晶体管耦合到所述半导体结构内的触点，使得上拉晶体管通过半导体结构的寄生电阻耦合到电压输入。 公开了另外的实施例。

    Protected substrate structure for a field emission dispaly device
    13.
    发明申请
    Protected substrate structure for a field emission dispaly device 审中-公开
    用于场发射观测装置的受保护的衬底结构

    公开(公告)号：US20060108912A1

    公开(公告)日：2006-05-25

    申请号：US11326266

    申请日：2005-12-30

    Applicant: Bob Mackey ,  Duane Haven ,  Arthur Learn ,  John Porter ,  Theodore Fahlen ,  Shiyou Pei ,  William Cummings

    Inventor： Bob Mackey ,  Duane Haven ,  Arthur Learn ,  John Porter ,  Theodore Fahlen ,  Shiyou Pei ,  William Cummings

    IPC: H01J1/62

    CPC classification number: H01J29/94 ,  H01J1/304 ,  H01J29/06 ,  H01J29/085 ,  H01J2201/02 ,  H01J2329/00 ,  H01J2329/863 ,  H01J2329/8645 ,  H01J2329/8665

    Abstract: A protected faceplate structure of a field emission display device is disclosed in one embodiment. Specifically, in one embodiment, the present invention recites a faceplate of a field emission display device wherein the faceplate of the field emission display device is adapted to have phosphor containing wells disposed above one side thereof. The present embodiment is further comprised of a barrier layer which is disposed over the one side of said faceplate which is adapted to have phosphor containing wells disposed thereabove. The barrier layer of the present embodiment is adapted to prevent degradation of the faceplate. Specifically, the barrier layer of the present embodiment is adapted to prevent degradation of the faceplate due to electron bombardment by electrons directed towards the phosphor containing wells.

    Abstract translation: 在一个实施例中公开了场致发射显示装置的受保护的面板结构。 具体地说，在一个实施例中，本发明叙述了场致发射显示装置的面板，其中场致发射显示装置的面板适于在其一侧上设置含荧光体的孔。 本实施例还包括设置在所述面板的一侧上的阻挡层，其适于具有设置在其上的荧光体含有孔。 本实施例的阻挡层适于防止面板的劣化。 具体地说，本实施例的阻挡层适于防止由于电子被引向含荧光体孔的电子轰击导致面板的劣化。

    Synchronization in a communication system
    17.
    发明申请
    Synchronization in a communication system 有权
    通信系统中的同步

    公开(公告)号：US20050175037A1

    公开(公告)日：2005-08-11

    申请号：US10510406

    申请日：2003-04-03

    Applicant: John Porter ,  Benedict Freeman

    Inventor： John Porter ,  Benedict Freeman

    IPC: H04J3/06 ,  H04L12/54 ,  H04L12/70 ,  H04Q11/04

    CPC classification number: H04L12/5601 ,  H04J3/0632 ,  H04J3/0658 ,  H04J2203/0035 ,  H04J2203/005 ,  H04L2012/5607 ,  H04L2012/5616 ,  H04L2012/5649 ,  H04L2012/5652

    Abstract: A packet switched communications system for transmitting synchronous data from a source module (4) to a terminating module (8) over a network comprises plurality of modules (4, 5, 7, 8) interconnected via transmission links (2, 6, 9). Each module operates with a clock of nominal frequency but which is not synchronised with the clocks of the other module(s) and has a single input and one or more outputs where all the outputs are phase locked to each other but are not synchronised with respect to the input. The system includes means (405, 504) for determining the accumulated phase difference between the input clock and the output clock of each module, and means (5, 7) for transmitting the accumulated phase difference to the terminating module (8) in the network. The received accumulated phase difference at the terminating module (8) is used to lock the output clock at the terminating module to the input clock at the source module.

    Abstract translation: 用于通过网络从源模块（4）向终端模块（8）发送同步数据的分组交换通信系统包括通过传输链路（2,6,9）互连的多个模块（4,5,7,8） 。 每个模块以标称频率的时钟运行，但不与其他模块的时钟同步，并且具有单个输入和一个或多个输出，其中所有输出彼此相位锁定，但不相关 到输入。 该系统包括用于确定每个模块的输入时钟和输出时钟之间的累积相位差的装置（405,504），以及用于将累积的相位差发送到网络中的终端模块（8）的装置（5,7） 。 在端接模块（8）处接收到的累积相位差用于将端接模块处的输出时钟锁定到源模块的输入时钟。

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