公开(公告)号：US07678692B2

公开(公告)日：2010-03-16

申请号：US11564238

申请日：2006-11-28

Applicant: Yi-Nan Chen ,  Jeng-Ping Lin ,  Chih-Ching Lin ,  Hui-Min Mao

Inventor： Yi-Nan Chen ,  Jeng-Ping Lin ,  Chih-Ching Lin ,  Hui-Min Mao

IPC: H01L21/4763

CPC classification number: H01L21/76897 ,  H01L21/76885 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10888

Abstract: A fabrication method for a damascene bit line contact plug. A semiconductor substrate has a first gate conductive structure, a second gate conductive structure and a source/drain region formed therebetween. A first conductive layer is formed in a space between the first gate conductive structure and the second gate conductive structure to be electrically connected to the source/drain region. An inter-layer dielectric with a planarized surface is formed to cover the first conductive layer, the first gate conductive structure, and the second gate conductive structure. A bit line contact hole is formed in the inter-layer dielectric to expose the top of the first conductive layer. A second conductive layer is formed in the bit line contact hole, in which the combination of the second conductive layer and the first conductive layer serves as a damascene bit line contact plug.

Abstract translation: 镶嵌位线接触插头的制造方法。 半导体衬底具有形成在其间的第一栅极导电结构，第二栅极导电结构和源极/漏极区。 第一导电层形成在第一栅极导电结构和第二栅极导电结构之间的空间中，以电连接到源极/漏极区。 形成具有平坦化表面的层间电介质以覆盖第一导电层，第一栅极导电结构和第二栅极导电结构。 在层间电介质中形成位线接触孔，露出第一导电层的顶部。 第二导电层形成在位线接触孔中，其中第二导电层和第一导电层的组合用作镶嵌位线接触插塞。

公开(公告)号：US20050202671A1

公开(公告)日：2005-09-15

申请号：US10908824

申请日：2005-05-27

Applicant: Tse-Yao Huang ,  Yi-Nan Chen ,  Chih-Ching Lin

Inventor： Tse-Yao Huang ,  Yi-Nan Chen ,  Chih-Ching Lin

IPC: H01L21/3205 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/76 ,  H01L21/768

CPC classification number: H01L21/7685 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76837

Abstract: A method for fabricating interconnects is provided. The method comprises forming a conducting line on a first dielectric layer; forming a first liner layer on the surfaces of the first dielectric layer and the conducting line; forming a second liner layer on the first liner layer; forming a second dielectric layer on the second liner layer, wherein the etching selectivity rate of the second dielectric layer is higher than the etching selectivity rate of the second liner; and patterning the second dielectric layer to form a contact window opening through the second liner layer and the first liner layer to expose the surface of the conducting line. Because the second dielectric layer having an etching rate higher than the etching rate of the second liner layer, the second liner layer can be used as an etch stop layer while patterning the second dielectric layer.

Abstract translation: 提供一种用于制造互连的方法。 该方法包括在第一电介质层上形成导线; 在所述第一介电层和所述导电线的表面上形成第一衬里层; 在所述第一衬里层上形成第二衬里层; 在所述第二衬里层上形成第二电介质层，其中所述第二电介质层的蚀刻选择率高于所述第二衬垫的蚀刻选择率; 以及图案化所述第二电介质层以形成穿过所述第二衬垫层和所述第一衬里层的接触窗口，以露出所述导电线的表面。 由于第二电介质层的蚀刻速率高于第二衬垫层的蚀刻速率，所以第二衬里层可以用作蚀刻停止层，同时构图第二介电层。

公开(公告)号：US06586324B2

公开(公告)日：2003-07-01

申请号：US10057085

申请日：2002-01-25

Applicant: Tse-Yao Huang ,  Chih-Ching Lin ,  Yu-Chi Sun ,  Chang Rong Wu ,  Shing-Yih Shih

Inventor： Tse-Yao Huang ,  Chih-Ching Lin ,  Yu-Chi Sun ,  Chang Rong Wu ,  Shing-Yih Shih

IPC: H01L214763

CPC classification number: H01L21/76837 ,  H01L21/76834

Abstract: A method of forming interconnects. An oxide masking layer with patterns is formed overlaying the metal layer. The patterns of the masking layer are transferred into the metal layer so as to form an opening. Then, a silicon nitride liner is conformally formed on the masking layer, the metal layer and the first insulating layer. Next, the silicon nitride liner and the masking layer are partially removed by reactive ion etching to leave a facet mask to reduce the aspect ratio of the opening followed by removal of the remaining silicon nitride liner. Then, an insulating layer is deposited to fill the opening.

Abstract translation: 形成互连的方法。 形成具有图案的氧化物掩模层，覆盖金属层。 将掩模层的图案转移到金属层中以形成开口。 然后，在掩模层，金属层和第一绝缘层上共形地形成氮化硅衬垫。 接下来，通过反应离子蚀刻部分去除氮化硅衬垫和掩模层以留下刻面掩模以减小开口的纵横比，随后除去剩余的氮化硅衬垫。 然后，沉积绝缘层以填充开口。

公开(公告)号：US20130037934A1

公开(公告)日：2013-02-14

申请号：US13205648

申请日：2011-08-09

Applicant: Chih-Ching Lin ,  Ya-Ting Chang ,  Chia-Lin Chuang

Inventor： Chih-Ching Lin ,  Ya-Ting Chang ,  Chia-Lin Chuang

IPC: H01L23/48

CPC classification number: H01L23/5286 ,  H01L23/5223 ,  H01L24/05

Abstract: An integrated circuit chip includes a power/ground interconnection network in a topmost metal layer over a semiconductor substrate and at least a bump pad on/over the power/ground interconnection network. The power/ground mesh interconnection network includes a first power/ground line connected to the bump pad and extending along a first direction, and a connection portion connected to the bump pad and extending along a second direction.

Abstract translation: 集成电路芯片包括位于半导体衬底上的最顶层金属层中的电源/接地互连网络，以及至少在电力/接地互连网络上/之上的凸块焊盘。 电源/接地网状互连网络包括连接到凸块焊盘并沿着第一方向延伸的第一电源/接地线，以及连接到凸块焊盘并沿第二方向延伸的连接部分。

公开(公告)号：US20130017687A1

公开(公告)日：2013-01-17

申请号：US13183358

申请日：2011-07-14

Applicant: Chih-Ching Lin ,  Yi-Nan Chen ,  Hsien-Wen Liu

Inventor： Chih-Ching Lin ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC: H01L21/306

CPC classification number: H01L21/76802 ,  H01L21/31144 ,  H01L21/32137

Abstract: A method for forming an opening in a semiconductor device is provided, including: providing a semiconductor substrate with a silicon oxide layer, a polysilicon layer and a silicon nitride layer sequentially formed thereover; patterning the silicon nitride layer, forming a first opening in the silicon nitride layer, wherein the first opening exposes a top surface of the polysilicon layer; performing a first etching process, using gasous etchants including hydrogen bromide (HBr), oxygen (O2), and fluorocarbons (CxFy), forming a second opening in the polysilicon layer, wherein a sidewall of the polysilicon layer adjacent to the second opening is substantially perpendicular to a top surface of the silicon oxide layer, wherein x is between 1-5 and y is between 2-8; removing the silicon nitride layer; and performing a second etching process, forming a third opening in the silicon oxide layer exposed by the second opening.

Abstract translation: 提供了一种在半导体器件中形成开口的方法，包括：向半导体衬底提供其上顺序形成的氧化硅层，多晶硅层和氮化硅层; 图案化氮化硅层，在氮化硅层中形成第一开口，其中第一开口暴露多晶硅层的顶表面; 使用包括溴化氢（HBr），氧（O 2）和碳氟化合物（C x F y）的气体蚀刻剂进行第一蚀刻工艺，在多晶硅层中形成第二开口，其中与第二开口相邻的多晶硅层的侧壁基本上 垂直于氧化硅层的顶表面，其中x在1-5之间，y在2-8之间; 去除氮化硅层; 以及进行第二蚀刻工艺，在由所述第二开口暴露的所述氧化硅层中形成第三开口。

公开(公告)号：US20120056488A1

公开(公告)日：2012-03-08

申请号：US13298315

申请日：2011-11-17

Applicant: Shen-Yu Huang ,  Chih-Ching Lin

Inventor： Shen-Yu Huang ,  Chih-Ching Lin

IPC: H02J1/02 ,  H05K3/00

CPC classification number: H01L27/0207 ,  H01L23/5223 ,  H01L23/5286 ,  H01L28/20 ,  H01L2924/0002 ,  H03K19/00346 ,  H01L2924/00

Abstract: A digital circuit block includes first to fourth conducting segments, a digital logic, first and second conducting layers, and a dielectric layer. The first and second conducting segments are coupled to first and second supply voltages, respectively. The digital logic and dielectric layer are between the first and second conducting segments. The third conducting segment includes a first end electrically connected to the first conducting segment, a second end not electrically connected to the second conducting segment, and a first portion located at the first conducting layer. The fourth conducting segment includes a first end electrically connected to the second conducting segment, a second end not electrically connected to the first conducting segment, and a second portion located at the second conducting layer. The first and second portions and dielectric layer are formed a first capacitive element to reduce the supply voltage drop between the first and second supply voltages.

Abstract translation: 数字电路块包括第一至第四导电段，数字逻辑，第一和第二导电层以及电介质层。 第一和第二导电段分别耦合到第一和第二电源电压。 数字逻辑和电介质层位于第一和第二导电段之间。 第三导电段包括电连接到第一导电段的第一端，不电连接到第二导电段的第二端和位于第一导电层的第一部分。 第四导电段包括电连接到第二导电段的第一端，不电连接到第一导电段的第二端和位于第二导电层的第二部分。 第一和第二部分和电介质层形成第一电容元件以减小第一和第二电源电压之间的电源电压降。

公开(公告)号：US20090249273A1

公开(公告)日：2009-10-01

申请号：US12060298

申请日：2008-04-01

Applicant: Tung-Kai Tsai ,  Chih-Ching Lin

Inventor： Tung-Kai Tsai ,  Chih-Ching Lin

IPC: G06F17/50 ,  H03K19/003

CPC classification number: G06F17/5068 ,  G06F2217/72 ,  H01L27/0207 ,  H01L27/11807

Abstract: A layout circuit is provided, comprising standard cells, a spare cell, combined tie cells and normal filler cells. The standard cells are disposed and routed on a layout area. The spare cell is added on the layout area and provided for replacing one of the standard cells while adding or changing functions later. The combined tie cells are added on the layout area. The normal filler cells are added on the rest of the layout area. The combined tie cell comprises a tie-high circuit, a tie-low circuit and a capacitance circuit. Some standard cells are disposed near at least one combined tie cell for avoiding routing congestion between the combined tie cells and the replaced standard cell. A circuit layout method is also provided.

Abstract translation: 提供了一种布局电路，包括标准单元，备用单元，组合连接单元和普通填充单元。 标准单元被布置并布置在布局区域上。 在布局区域中添加备用单元，并在稍后添加或更改功能时提供替换其中一个标准单元。 组合的领带单元被添加在布局区域上。 正常填充单元被添加到布局区域的其余部分。 组合式连接单元包括连接高电路，连接低电路和电容电路。 一些标准单元设置在至少一个组合的连接单元附近，以避免组合连接单元与替换的标准单元之间的路由拥塞。 还提供了电路布局方法。

公开(公告)号：US20050048761A1

公开(公告)日：2005-03-03

申请号：US10646896

申请日：2003-08-25

Applicant: Chih-Ching Lin ,  Yi-Nan Chen

Inventor： Chih-Ching Lin ,  Yi-Nan Chen

IPC: H01L21/44 ,  H01L21/4763 ,  H01L21/768

CPC classification number: H01L21/7685 ,  H01L21/76802 ,  H01L21/76865

Abstract: Disclosed is a method for forming conducting wire and contact opening in a semiconductor device. The method comprises steps of providing a substrate; forming a first dielectric layer on the substrate; digging a via in the first dielectric layer and filling metal therein; forming a conductor layer on the first dielectric including the via; forming a metal layer on the conductor layer; removing unnecessary portions of the conductor/metal layers to define recesses, with the left portions to form conducting wires; applying a second dielectric layer to fill the recesses and performing planarization thereto to expose the conducting wires; forming a third dielectric layer; forming photoresist of predetermined pattern on the third dielectric layer; removing predetermined portion of the third dielectric layer to form a contact opening; and removing the photoresist.

Abstract translation: 公开了一种在半导体器件中形成导线和接触开口的方法。 该方法包括提供衬底的步骤; 在所述基板上形成第一电介质层; 在第一电介质层中挖掘通孔并在其中填充金属; 在包括通孔的第一电介质上形成导体层; 在导体层上形成金属层; 去除导体/金属层的不需要的部分以限定凹部，其中左部分形成导线; 施加第二电介质层以填充凹部并对其进行平坦化以暴露导线; 形成第三电介质层; 在所述第三介电层上形成预定图案的光致抗蚀剂; 去除所述第三电介质层的预定部分以形成接触开口; 并去除光致抗蚀剂。

公开(公告)号：US06468908B1

公开(公告)日：2002-10-22

申请号：US09900406

申请日：2001-07-09

Applicant: Cheng-Shien Chen ,  Li-Der Chen ,  Chih-Min Wen ,  Chung Liu ,  Chih-Ching Lin

Inventor： Cheng-Shien Chen ,  Li-Der Chen ,  Chih-Min Wen ,  Chung Liu ,  Chih-Ching Lin

IPC: H01L2144

CPC classification number: H01L21/2855 ,  H01L21/32051 ,  H01L21/76838

Abstract: This invention relates to a method of fabricating metal wiring, whereby sputtered metal is rapidly cooled down by a post-metal quenching process, to prevent deleterious CuAl2 precipitation. The main embodiments are the formation of a TiN reactively sputtered bottom barrier layer, followed by a sputtered Al—Cu alloy wiring layer immediately followed by an in situ post-metal quench (key step), then followed by a reactively sputtered second TiN top barrier layer. The “in situ” post-metal quench is especially effective by employing wafer backside cooling using low temperature helium gas or argon gas, cooling the substrate from a high temperature range of 450 to 150 °C., to a low temperature range near room temperature, in a short time interval of between 30 to 180 seconds. The CuAl2 precipitates if allowed to form, block the etch removal of the underlying TiN layer causing electrical shorts between closely spaced lines.

Abstract translation: 本发明涉及一种制造金属布线的方法，其中溅射金属通过金属后淬火工艺快速冷却，以防止有害的CuAl 2沉淀。 主要实施方案是形成TiN反应溅射的底部阻挡层，随后是溅射的Al-Cu合金布线层，紧接着是原位金属后淬火（关键步骤），然后是反应溅射的第二TiN顶部阻挡层 层。 通过使用低温氦气或氩气的晶片背面冷却，“原位”后金属淬火特别有效，将基板从450至150℃的高温范围内冷却至接近室温的低温范围 ，在30到180秒的短时间间隔内。 如果允许形成CuAl2则沉淀，阻止下面的TiN层的蚀刻去除，导致紧密间隔的线之间的电短路。

公开(公告)号：US5553711A

公开(公告)日：1996-09-10

申请号：US498662

申请日：1995-07-03

Applicant: Chih-Ching Lin ,  Jin-Chys Tai

Inventor： Chih-Ching Lin ,  Jin-Chys Tai

IPC: H01L21/673 ,  B65D85/30

CPC classification number: H01L21/67369 ,  H01L21/67386

Abstract: A wafer container having an enclosure member and a body member. The body member having a base, a plurality of spaced arcuate members on the base adapted to encircle wafers stacked on the base. A layer of resilient material on the insides of the arcuate members. A retainer member with flaps positioned between the arcuate members on the top of a stack of wafers.

Abstract translation: 具有封闭构件和主体构件的晶片容器。 主体构件具有基部，在基部上的多个间隔开的弧形构件，适于围绕堆叠在基部上的晶片。 一层弹性材料在弧形构件的内侧。 具有位于一叠晶片顶部的弧形构件之间的翼片的保持构件。