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公开(公告)号：US10685879B1
公开(公告)日：2020-06-16
申请号：US16541873
申请日：2019-08-15
发明人： John C. Arnold , Ashim Dutta , Dominik Metzler , Takeshi Nogami
IPC分类号： H01L21/768 , H01L23/522 , H01L23/528
摘要： A method for fabricating a semiconductor device includes forming misalignment tolerant vias each having a landing area configured to account for alignment mismatch resulting from subsequent formation of conductive structures, depositing a conductive layer over the misalignment tolerant vias, and obtaining conductive layer patterning including each of the conductive structures formed on at least a portion of a respective one of the landing areas, including subtractively patterning the conductive layer. The misalignment tolerant vias and the conductive structures imparting a semiconductor device geometry accounting for the alignment mismatch.
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公开(公告)号：US10580652B2
公开(公告)日：2020-03-03
申请号：US16058088
申请日：2018-08-08
发明人： John C. Arnold , Anuja E. DeSilva , Nelson M. Felix , Chi-Chun Liu , Yann A. M. Mignot , Stuart A. Sieg
IPC分类号： H01L21/033 , H01L21/308 , H01L21/311 , H01L21/3213 , H01L29/66 , H01L21/8234
摘要： Methods of forming fins include masking a region on a three-color hardmask fin pattern, leaving a fin of a first color exposed. The exposed fin of the first color is etched away with a selective etch that does not remove fins of a second color or a third color. The mask and all fins of a second color are etched away. Fins are etched into a fin base layer using the fins of the first color and the fins of the third color.
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13.发明申请公开(公告)号：US20190164773A1
公开(公告)日：2019-05-30
申请号：US15824175
申请日：2017-11-28
发明人： John C. Arnold , Robert L. Bruce , Sebastian U. Engelmann , Nathan P. Marchack , Hiroyuki Miyazoe , Jeffrey C. Shearer , Takefumi Suzuki
IPC分类号： H01L21/311 , H01L21/768
摘要： A method of forming field effect transistor (FET) circuits, and forming Integrated Circuit (IC) chips with the FET circuits. After forming gate sidewall spacers, filling with insulation and planarizing to the top of the sidewall spacers, self-aligned source/drain contacts are etched through the insulation and said gate dielectric layer to source/drain regions. A combination fluoroether/hydrofluoroether-hydrofluorocarbon (*FE-HFC) plasma etch etches the source/drain contacts self-aligned. The self-aligned contacts are filled with conductive material, and FETs are wired together into circuits, connecting to FETs through the self-aligned contacts.
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公开(公告)号：US10833258B1
公开(公告)日：2020-11-10
申请号：US16402126
申请日：2019-05-02
摘要： MRAM devices with in-situ encapsulation are provided. In one aspect, a method of forming an MRAM device includes: patterning an MRAM stack disposed on a dielectric into individual memory cell stacks, wherein the MRAM stack includes a bottom electrode, a MTJ, and a top electrode, and wherein the patterning is performed using an intermediate angle IBE landing on the dielectric; removing redeposited metal from the memory cell stacks using a high angle IBE; redepositing the dielectric along the sidewalls of the memory cell stacks using a low angle IBE to form a first layer of dielectric encapsulating the memory cell stacks; and depositing a second layer of dielectric, wherein the first/second layers of dielectric form a bilayer dielectric spacer structure, wherein the patterning, removing of the redeposited metal, and redepositing the dielectric steps are all performed in-situ. An MRAM device is also provided.
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15.发明授权公开(公告)号：US10833257B1
公开(公告)日：2020-11-10
申请号：US16401960
申请日：2019-05-02
摘要： Techniques are provided for fabricating semiconductor integrated circuit devices with embedded magnetic random-access memory (MRAM) devices. For example, a MRAM device and a multi-level bottom electrode via contact are formed within a back-end-of line layer. The MRAM device includes a memory device pillar having a bottom electrode, a magnetic tunnel junction structure, and an upper electrode. The multi-level bottom electrode via contact is disposed below and in contact with the bottom electrode. The multi-level bottom electrode via contact includes a first via contact disposed in a first insulation layer, and a second via contact disposed in a second insulation layer. The first and second insulation layers allow for sacrificial etching of the first and second insulation layers during formation of the MRAM device while retaining a sufficient thickness of remaining insulation material to serve as a capping layer to protect metallic wiring that is disposed in an underlying metallization layer.
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公开(公告)号：US20200350495A1
公开(公告)日：2020-11-05
申请号：US16402126
申请日：2019-05-02
摘要： MRAM devices with in-situ encapsulation are provided. In one aspect, a method of forming an MRAM device includes: patterning an MRAM stack disposed on a dielectric into individual memory cell stacks, wherein the MRAM stack includes a bottom electrode, a MTJ, and a top electrode, and wherein the patterning is performed using an intermediate angle IBE landing on the dielectric; removing redeposited metal from the memory cell stacks using a high angle IBE; redepositing the dielectric along the sidewalls of the memory cell stacks using a low angle IBE to form a first layer of dielectric encapsulating the memory cell stacks; and depositing a second layer of dielectric, wherein the first/second layers of dielectric form a bilayer dielectric spacer structure, wherein the patterning, removing of the redeposited metal, and redepositing the dielectric steps are all performed in-situ. An MRAM device is also provided.
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17.发明申请公开(公告)号：US20200350494A1
公开(公告)日：2020-11-05
申请号：US16401960
申请日：2019-05-02
摘要： Techniques are provided for fabricating semiconductor integrated circuit devices with embedded magnetic random-access memory (MRAM) devices. For example, a MRAM device and a multi-level bottom electrode via contact are formed within a back-end-of line layer. The MRAM device includes a memory device pillar having a bottom electrode, a magnetic tunnel junction structure, and an upper electrode. The multi-level bottom electrode via contact is disposed below and in contact with the bottom electrode. The multi-level bottom electrode via contact includes a first via contact disposed in a first insulation layer, and a second via contact disposed in a second insulation layer. The first and second insulation layers allow for sacrificial etching of the first and second insulation layers during formation of the MRAM device while retaining a sufficient thickness of remaining insulation material to serve as a capping layer to protect metallic wiring that is disposed in an underlying metallization layer.
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公开(公告)号：US20200144491A1
公开(公告)日：2020-05-07
申请号：US16719164
申请日：2019-12-18
发明人： Michael Rizzolo , Daniel C. Edelstein , Theodorus E. Standaert , Kisup Chung , Isabel C. Chu , John C. Arnold
摘要： Multilayered hardmask structures are provided which can prevent degradation of the performance of a magnetic tunnel junction (MTJ) structure. The multilayered hardmask structures include at least a halogen barrier hardmask layer and an upper hardmask layer. The halogen barrier hardmask layer can prevent halogen ions that are used to pattern the upper hardmask layer from diffusing into the MTJ structure.
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公开(公告)号：US10304692B1
公开(公告)日：2019-05-28
申请号：US15824175
申请日：2017-11-28
发明人： John C. Arnold , Robert L. Bruce , Sebastian U. Engelmann , Nathan P. Marchack , Hiroyuki Miyazoe , Jeffrey C. Shearer , Takefumi Suzuki
IPC分类号： H01L21/336 , H01L21/311 , H01L21/768 , H01L21/8234
摘要： A method of forming field effect transistor (FET) circuits, and forming Integrated Circuit (IC) chips with the FET circuits. After forming gate sidewall spacers, filling with insulation and planarizing to the top of the sidewall spacers, self-aligned source/drain contacts are etched through the insulation and said gate dielectric layer to source/drain regions. A combination fluoroether/hydrofluoroether-hydrofluorocarbon (*FE-HFC) plasma etch etches the source/drain contacts self-aligned. The self-aligned contacts are filled with conductive material, and FETs are wired together into circuits, connecting to FETs through the self-aligned contacts.
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公开(公告)号：US10242872B2
公开(公告)日：2019-03-26
申请号：US15464758
申请日：2017-03-21
发明人： John C. Arnold , Prasad Bhosale , Donald F. Canaperi , Raghuveer R. Patlolla , Cornelius B. Peethala , Hosadurga Shobha , Theodorus E. Standaert
IPC分类号： H01L21/302 , H01L21/033 , H01L21/3105 , H01L21/311 , H01L21/66 , H01L21/768 , H01L21/3213
摘要： A method for reworking a semiconductor device includes, in a pattern stack formed on an interlevel dielectric (ILD) layer, polishing the pattern stack to remove a top hardmask layer of the pattern stack. Each hardmask layer of the pattern stack is selectively wet etched to remaining layers of the pattern stack and the ILD layer. A reworked pattern stack is reformed on the ILD layer.
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