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公开(公告)号：US11923246B2
公开(公告)日：2024-03-05
申请号：US17475463
申请日：2021-09-15
IPC分类号： H01L21/768 , H01L23/522 , H01L23/528
CPC分类号： H01L21/76897 , H01L21/76816 , H01L21/76885 , H01L23/5226 , H01L23/528
摘要： A method of via formation including forming a sacrificial mask over a conductive layer, forming a plurality of pillars in the sacrificial mask and the conductive layer, wherein each pillar of the plurality of pillars includes a sacrificial cap and a first conductive via, depositing a spacer between the plurality of pillars, masking at least one of the sacrificial caps, removing at least one of the sacrificial caps to create openings, forming second conductive vias in the openings, and depositing a dielectric coplanar to a top surface of the second conductive vias.
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公开(公告)号：US20220109099A1
公开(公告)日：2022-04-07
申请号：US17552027
申请日：2021-12-15
摘要： A method for fabricating a semiconductor device includes forming a conductive shell layer along a memory stack and a patterned hardmask disposed on the memory stack, and etching the patterned hardmask, the conductive shell layer and the memory stack to form a structure including a central core surrounded by a conductive outer shell disposed on a patterned memory stack.
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公开(公告)号：US20210242277A1
公开(公告)日：2021-08-05
申请号：US16780684
申请日：2020-02-03
摘要： Techniques for integrating an embedded MRAM device with a BEOL interconnect structure are provided. In one aspect, a method of forming an embedded MRAM device includes: depositing a cap layer onto a substrate; forming a metal line and metal pad on the cap layer; patterning the metal line to form first top vias, and the metal pad to form a second top via; depositing a dielectric material onto the substrate surrounding the first/second top vias; recessing the second top via to form a bottom contact via self-aligned to the metal pad which serves as a bottom contact; forming an MRAM cell over the bottom contact via; and forming first/second top contacts in contact with the first top vias/the MRAM cell. An embedded MRAM device is also provided.
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公开(公告)号：US20230186962A1
公开(公告)日：2023-06-15
申请号：US17644349
申请日：2021-12-15
IPC分类号： G11C11/16 , H01L27/22 , H01L43/10 , H01L43/08 , H01L43/02 , H01L43/12 , H01L23/522 , H01L21/768
CPC分类号： G11C11/161 , H01L27/222 , H01L43/10 , H01L43/08 , H01L43/02 , H01L43/12 , H01L23/5226 , H01L21/76816
摘要： A memory device with modified top electrode contact includes a memory pillar composed of a bottom electrode, a magnetic random-access memory (MRAM) stack above the bottom electrode, and a top electrode above the MRAM stack. A first portion of an encapsulation layer is disposed along opposite sidewalls of the bottom electrode, on opposite sidewalls of the MRAM stack and on opposite sidewalls of a bottom portion of the top electrode, a second portion of the encapsulation layer is located above a second dielectric layer. A metal cap is located above an uppermost surface and opposite sidewalls of a top portion of the top electrode and above an uppermost surface of the first portion of the encapsulation layer. A second conductive interconnect is formed above a top surface of the metal cap wrapping around opposite sidewalls of the first portion of the encapsulation layer and opposite sidewalls of the metal cap.
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公开(公告)号：US20230084739A1
公开(公告)日：2023-03-16
申请号：US17447388
申请日：2021-09-10
IPC分类号： H01L21/3213 , H01L21/768
摘要： A method of making a back-end-of-line (BEOL) component includes filling spaces in a layer of metal material and a layer of hardmask material with a layer of scaffolding material. The method further includes forming at least one plug on top of the layer of metal material such that the at least one plug is integrally formed with the layer of scaffolding material. The method further includes removing the layer of hardmask material such that a top surface of the layer of metal material is exposed except where the at least one plug is formed on top of the layer of metal material. The method further includes recessing the layer of metal material where the top surface of the layer of metal material is exposed. The method further includes removing the scaffolding material.
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公开(公告)号：US11244907B2
公开(公告)日：2022-02-08
申请号：US16732531
申请日：2020-01-02
IPC分类号： H01L23/544 , G03F9/00
摘要： Methods and structures for improving alignment contrast for patterning a metal layer generally includes depositing a metal layer having a plurality of grains, wherein grain boundaries between the grains forms grooves at a surface of the metal layer. The metal layer is subjected to surface treatment to form an oxide or a nitride layer and fill the surface grooves. The metal layer can be patterned using alignment marks in the metal layer and/or underlying layers. Filling the grooves with the oxide or nitride increases alignment contrast relative to patterning the metal layer without the surface treating.
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公开(公告)号：US11189527B2
公开(公告)日：2021-11-30
申请号：US16826944
申请日：2020-03-23
发明人： Timothy Mathew Philip , Sagarika Mukesh , Dominik Metzler , Ashim Dutta , John Christopher Arnold
IPC分类号： H01L23/48 , H01L21/768 , H01L23/528 , H01L23/522
摘要： A method includes forming a plurality of elongated dielectric members on a semiconductor substrate. The elongated dielectric members each extend vertically from the semiconductor substrate and define opposed vertical walls. The method further includes forming opposed spacer walls on the vertical walls of the elongated dielectric members. Adjacent spacer walls of longitudinally adjacent elongated dielectric members define first trenches therebetween. The method also includes depositing a first metal material within the first trenches to form a first set of first metal lines, removing the elongated dielectric members to define second trenches between the opposed spacer walls on the opposed vertical walls of each elongated dielectric member, and depositing a second metal material within the second trenches to form a second set of second metal lines. The first and second metal lines of the first and second sets are disposed in alternating arrangement.
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公开(公告)号：US11830807B2
公开(公告)日：2023-11-28
申请号：US17499123
申请日：2021-10-12
IPC分类号： H01L23/522 , H01L23/528 , H01L21/768
CPC分类号： H01L23/5226 , H01L21/76816 , H01L21/76879 , H01L21/76897 , H01L23/5283
摘要： Embodiments of the present invention are directed to fabrication method and resulting structures for placing self-aligned top vias at line ends of an interconnect structure. In a non-limiting embodiment of the invention, a line feature is formed in a metallization layer of an interconnect structure. The line feature can include a line hard mask. A trench is formed in the line feature to expose line ends of the line feature. The trench is filled with a host material and a growth inhibitor is formed over a first line end of the line feature. A via mask is formed over a second line end of the line feature. The via mask can be selectively grown on an exposed surface of the host material. Portions of the line feature that are not covered by the via mask are recessed to define a self-aligned top via at the second line end.
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公开(公告)号：US20230078008A1
公开(公告)日：2023-03-16
申请号：US17475463
申请日：2021-09-15
IPC分类号： H01L21/768 , H01L23/522 , H01L23/528
摘要： A method of via formation including forming a sacrificial mask over a conductive layer, forming a plurality of pillars in the sacrificial mask and the conductive layer, wherein each pillar of the plurality of pillars includes a sacrificial cap and a first conductive via, depositing a spacer between the plurality of pillars, masking at least one of the sacrificial caps, removing at least one of the sacrificial caps to create openings, forming second conductive vias in the openings, and depositing a dielectric coplanar to a top surface of the second conductive vias.
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公开(公告)号：US11205678B2
公开(公告)日：2021-12-21
申请号：US16780684
申请日：2020-02-03
摘要： Techniques for integrating an embedded MRAM device with a BEOL interconnect structure are provided. In one aspect, a method of forming an embedded MRAM device includes: depositing a cap layer onto a substrate; forming a metal line and metal pad on the cap layer; patterning the metal line to form first top vias, and the metal pad to form a second top via; depositing a dielectric material onto the substrate surrounding the first/second top vias; recessing the second top via to form a bottom contact via self-aligned to the metal pad which serves as a bottom contact; forming an MRAM cell over the bottom contact via; and forming first/second top contacts in contact with the first top vias/the MRAM cell. An embedded MRAM device is also provided.
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