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公开(公告)号:US09934984B2
公开(公告)日:2018-04-03
申请号:US14849077
申请日:2015-09-09
发明人: Robert L. Bruce , Eric A. Joseph , Joe Lee , Takefumi Suzuki
IPC分类号: H01L21/4763 , H01L21/302 , H01L21/311 , H01L21/768 , H01L23/528 , H01L23/532
CPC分类号: H01L21/31116 , H01L21/76802 , H01L21/76816 , H01L21/76877 , H01L23/528 , H01L23/5329
摘要: In one embodiment, a method for hydrofluorocarbon gas-assisted plasma etch for interconnect fabrication includes providing a layer of a dielectric material and etching a trench in the layer of the dielectric material, by applying a mixture of an aggressive dielectric etch gas and a polymerizing etch gas to the layer of the dielectric material. In another embodiment, an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices. A pitch of the plurality of conductive lines is approximately twenty-eight nanometers.
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公开(公告)号:US20190164773A1
公开(公告)日:2019-05-30
申请号:US15824175
申请日:2017-11-28
发明人: John C. Arnold , Robert L. Bruce , Sebastian U. Engelmann , Nathan P. Marchack , Hiroyuki Miyazoe , Jeffrey C. Shearer , Takefumi Suzuki
IPC分类号: H01L21/311 , H01L21/768
摘要: A method of forming field effect transistor (FET) circuits, and forming Integrated Circuit (IC) chips with the FET circuits. After forming gate sidewall spacers, filling with insulation and planarizing to the top of the sidewall spacers, self-aligned source/drain contacts are etched through the insulation and said gate dielectric layer to source/drain regions. A combination fluoroether/hydrofluoroether-hydrofluorocarbon (*FE-HFC) plasma etch etches the source/drain contacts self-aligned. The self-aligned contacts are filled with conductive material, and FETs are wired together into circuits, connecting to FETs through the self-aligned contacts.
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公开(公告)号:US20180122649A1
公开(公告)日:2018-05-03
申请号:US15847369
申请日:2017-12-19
发明人: Robert L. Bruce , Eric A. Joseph , Joe Lee , Takefumi Suzuki
IPC分类号: H01L21/311 , H01L23/532 , H01L23/528 , H01L21/768
CPC分类号: H01L21/31116 , H01L21/76802 , H01L21/76816 , H01L21/76877 , H01L23/528 , H01L23/5329
摘要: In one embodiment, a method for hydrofluorocarbon gas-assisted plasma etch for interconnect fabrication includes providing a layer of a dielectric material and etching a trench in the layer of the dielectric material, by applying a mixture of an aggressive dielectric etch gas and a polymerizing etch gas to the layer of the dielectric material. In another embodiment, an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices. A pitch of the plurality of conductive lines is approximately twenty-eight nanometers.
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公开(公告)号:US10304692B1
公开(公告)日:2019-05-28
申请号:US15824175
申请日:2017-11-28
发明人: John C. Arnold , Robert L. Bruce , Sebastian U. Engelmann , Nathan P. Marchack , Hiroyuki Miyazoe , Jeffrey C. Shearer , Takefumi Suzuki
IPC分类号: H01L21/336 , H01L21/311 , H01L21/768 , H01L21/8234
摘要: A method of forming field effect transistor (FET) circuits, and forming Integrated Circuit (IC) chips with the FET circuits. After forming gate sidewall spacers, filling with insulation and planarizing to the top of the sidewall spacers, self-aligned source/drain contacts are etched through the insulation and said gate dielectric layer to source/drain regions. A combination fluoroether/hydrofluoroether-hydrofluorocarbon (*FE-HFC) plasma etch etches the source/drain contacts self-aligned. The self-aligned contacts are filled with conductive material, and FETs are wired together into circuits, connecting to FETs through the self-aligned contacts.
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公开(公告)号:US20190013209A1
公开(公告)日:2019-01-10
申请号:US16130596
申请日:2018-09-13
发明人: Robert L. Bruce , Eric A. Joseph , Joe Lee , Takefumi Suzuki
IPC分类号: H01L21/311 , H01L21/768 , H01L23/532 , H01L23/528
摘要: In one embodiment, a method for hydrofluorocarbon gas-assisted plasma etch for interconnect fabrication includes providing a layer of a dielectric material and etching a trench in the layer of the dielectric material, by applying a mixture of an aggressive dielectric etch gas and a polymerizing etch gas to the layer of the dielectric material. In another embodiment, an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices. A pitch of the plurality of conductive lines is approximately twenty-eight nanometers.
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公开(公告)号:US10121676B2
公开(公告)日:2018-11-06
申请号:US15847369
申请日:2017-12-19
发明人: Robert L. Bruce , Eric A. Joseph , Joe Lee , Takefumi Suzuki
IPC分类号: H01L29/06 , H01L29/40 , H01L21/311 , H01L23/532 , H01L23/528 , H01L21/768
摘要: In one embodiment, a method for hydrofluorocarbon gas-assisted plasma etch for interconnect fabrication includes providing a layer of a dielectric material and etching a trench in the layer of the dielectric material, by applying a mixture of an aggressive dielectric etch gas and a polymerizing etch gas to the layer of the dielectric material. In another embodiment, an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices. A pitch of the plurality of conductive lines is approximately twenty-eight nanometers.
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