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公开(公告)号：US09843959B2
公开(公告)日：2017-12-12
申请号：US14872039
申请日：2015-09-30
Applicant: Intel IP Corporation
Inventor： Michael Kerner , Uri Parker , Avi Gazneli , Nati Dinur
CPC classification number: H04W28/0236 , H04J11/00 , H04W24/02 , H04W24/08 , H04W84/12
Abstract: Described herein are technologies related to an implementation for dynamic adjustment of an out-of-band emission in a wireless modem, including spurious emissions, such as a Wi-FI modem, to minimize interference on a collocated or co-running downlink reception of another wireless modem residing on the same device by dynamically adjustment of a power consumption.
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公开(公告)号：US10477476B2
公开(公告)日：2019-11-12
申请号：US15280350
申请日：2016-09-29
Applicant: Intel IP Corporation
Inventor： Michael Kerner , Uri Perlmutter , Avishay Friedman , Rotem Banin , Tzvi Maimon
Abstract: A wireless device and method of power consumption reduction are generally described herein. The wireless device may map a plurality of data symbols to sub-carriers for an orthogonal frequency division multiplexing (OFDM) transmission. The wireless device may divide the plurality of data symbols into first and second groups of data symbols. The wireless device may generate a first OFDM signal from the first group of data symbols for amplification by a first power amplifier (PA). The wireless device may generate a second OFDM signal from the second group of data symbols for amplification by a second PA. The data symbols of the first and second groups may be selected to provide a PAPR of the first OFDM signal that is lower than a PAPR of a composite OFDM signal based on the plurality of data symbols.
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公开(公告)号：US10263624B2
公开(公告)日：2019-04-16
申请号：US15634183
申请日：2017-06-27
Applicant: Intel IP Corporation
Inventor： Michael Kerner , Elan Banin , Yair Dgani , Evgeny Shumaker , Danniel Nahmanny , Gil Horovitz
Abstract: Systems, methods, and circuitries for synchronizing a first phase locked loop (PLL) with a second PLL are provided. In one example a PLL system includes a first PLL configured to generate a first signal; a second PLL configured to generate a second signal; and phase calculation circuitry. The phase calculation circuitry is configured to calculate a phase of the first signal at a given time; and provide the calculated phase to the second PLL for use by the second PLL in synchronizing a phase of the second with the phase of the first signal.
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公开(公告)号：US09935590B2
公开(公告)日：2018-04-03
申请号：US15256718
申请日：2016-09-05
Applicant: Intel IP Corporation
Inventor： Avi Sulimarski , Itay Almog , Michael Kerner
CPC classification number: H03F1/3258 , H03F1/3282 , H03F3/19 , H03F3/21 , H03F3/245 , H03F2200/336 , H03F2200/451 , H03F2201/3224 , H04B1/0475 , H04B2001/0425
Abstract: Techniques for compensating for signal impairments introduced by a mixer are discussed. One example system employing such techniques can include mixer predistortion circuitry configured to receive signal in-phase (I) and signal quadrature (Q) components of a signal and to generate a mixer predistortion signal based at least in part on the signal I and Q components, wherein the mixer predistortion signal compensates for nonlinearities caused by a mixer that upconverts the signal. Optionally, imbalance correction circuitry to compensate for gain and phase imbalance and/or skew correction circuitry to compensate for gain and phase skew can also be included.
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公开(公告)号：US20180091177A1
公开(公告)日：2018-03-29
申请号：US15274509
申请日：2016-09-23
Applicant: Intel IP Corporation
Inventor： Elan Banin , Uri Parker , Ofir Degani , Michael Kerner
CPC classification number: H04B1/0475 , H04B2001/0425 , H04L27/367
Abstract: Devices and methods of compensating for a bandpass filter are generally described. A DTx includes a BPF from which an output signal is produced and a DFE having a zero crossing (ZC) pre-distorter (ZCPD). The ZCPD compensates for ZC distortion from a desired analog signal caused by the BPF. The ZCPD adjusts a DTC code word to generate a DTx output signal to be applied to the BPF. The compensation is dependent on a magnitude of the square wave immediately prior to and after the ZC. The compensated DTC and a DPA code word are used to generate the DTx output signal. The compensation produced by the ZCPD is free from compensation for non-linear responses to the DTC and DPA code words.
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Patent Agency Ranking
公开(公告)号：US20170094551A1
公开(公告)日：2017-03-30
申请号：US14872039
申请日：2015-09-30
Applicant: Intel IP Corporation
Inventor： Michael Kerner , Uri Parker , Avi Gazneli , Nati Dinur
CPC classification number: H04W28/0236 , H04J11/00 , H04W24/02 , H04W24/08 , H04W84/12
Abstract: Described herein are technologies related to an implementation for dynamic adjustment of an out-of-band emission in a wireless modem, including spurious emissions, such as a Wi-FI modem, to minimize interference on a collocated or co-running downlink reception of another wireless modem residing on the same device by dynamically adjustment of a power consumption.
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公开(公告)号：US09438178B1
公开(公告)日：2016-09-06
申请号：US14843174
申请日：2015-09-02
Applicant: INTEL IP CORPORATION
Inventor： Avi Sulimarski , Itay Almog , Michael Kerner
CPC classification number: H03F1/3258 , H03F1/3282 , H03F3/19 , H03F3/21 , H03F3/245 , H03F2200/336 , H03F2200/451 , H03F2201/3224 , H04B1/0475 , H04B2001/0425
Abstract: Techniques for compensating for signal impairments introduced by a mixer are discussed. One example system employing such techniques can include mixer predistortion circuitry configured to receive signal in-phase (I) and signal quadrature (Q) components of a signal and to generate a mixer predistortion signal based at least in part on the signal I and Q components, wherein the mixer predistortion signal compensates for nonlinearities caused by a mixer that upconverts the signal. Optionally, imbalance correction circuitry to compensate for gain and phase imbalance and/or skew correction circuitry to compensate for gain and phase skew can also be included.
Abstract translation: 讨论了用于补偿由混合器引入的信号损伤的技术。 采用这种技术的一个示例系统可以包括配置成接收信号的信号同相（I）和信号正交（Q）分量的混合器预失真电路，并且至少部分地基于信号I和Q分量来产生混合器预失真信号 ，其中混频器预失真信号补偿由上变频信号的混频器引起的非线性。 可选地，还可以包括用于补偿增益和相位不平衡和/或偏斜校正电路以补偿增益和相位偏移的不平衡校正电路。
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公开(公告)号：US10686451B2
公开(公告)日：2020-06-16
申请号：US16465515
申请日：2016-12-30
Applicant: Intel IP Corporation
Inventor： Yair Dgani , Michael Kerner , Elan Banin , Nati Dinur , Gil Horovitz , Rotem Banin
Abstract: Aspects of a digital phase-lock loop (DPLL) with an adjustable delay between an output clock and a reference clock in accordance with phase noise compensation are generally described herein. An apparatus may include processing circuitry configured to, in a first mode, identify a delay element of a plurality of delay elements based on an associated delay value, and set an initial phase difference value to a phase difference value associated with the identified delay element. The processor circuitry may be further configured to, in a second mode, in a second mode, initialize the DPLL using the initial phase difference value, determine a phase error between a reference clock and a feedback clock based on the initial phase difference value, adjust an output clock signal based on the phase error.
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公开(公告)号：US10516562B2
公开(公告)日：2019-12-24
申请号：US15775845
申请日：2015-12-21
Applicant: Intel IP Corporation
Inventor： Itay Almog , Michael Kerner
Abstract: A communication device is provided that includes a modulation circuit configured to modulate a signal comprising a first signal portion of a first data type and a second signal portion of a second data type. The modulation circuit is configured to modulate the first signal portion in accordance with a first modulation scheme and the second signal portion in accordance with a second modulation scheme. At least one of the first data type is different from the second data type or the second modulation scheme is different from the first modulation scheme. The communication device further includes a modification circuit configured to modify the modulated first signal portion based on a first modification scheme and the second signal portion based on a second modification scheme. The communication device further includes a transmitter configured to transmit the modified first signal portion and the modified second signal portion.
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公开(公告)号：US10284332B2
公开(公告)日：2019-05-07
申请号：US15449078
申请日：2017-03-03
Applicant: Intel IP Corporation
Inventor： Rotem Avivi , Michael Kerner , Assaf Gurevitz
Abstract: A spur cancelation system includes error circuitry, inverse spur circuitry, and injection circuitry. The error circuitry is configured to generate an error signal based at least on a first transceiver signal in a transceiver signal processing chain. The inverse spur circuitry is configured to, based at least on the error signal, determine a gain and a phase of a spur signal in the transceiver signal and generate an inverse spur signal based at least on the gain and the phase of the spur signal. The injection circuitry is configured to inject the inverse spur signal to cancel a spur in a second transceiver signal in the transceiver signal processing chain.
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