公开(公告)号：US10649908B2

公开(公告)日：2020-05-12

申请号：US16281132

申请日：2019-02-21

Applicant: International Business Machines Corporation

Inventor： Ekaterina M. Ambroladze ,  Deanna P. D. Berger ,  Michael A. Blake ,  Pak-kin Mak ,  Robert J. Sonnelitter, III ,  Guy G. Tracy ,  Chad G. Wilson

IPC: G06F13/00 ,  G06F12/0891 ,  G06F12/0804 ,  G06F12/0864 ,  G06F12/0897

Abstract: In an approach for purging an address range from a cache, a processor quiesces a computing system. Cache logic issues a command to purge a section of a cache to higher level memory, wherein the command comprises a starting storage address and a range of storage addresses to be purged. Responsive to each cache of the computing system activating the command, cache logic ends the quiesce of the computing system. Subsequent to ending the quiesce of the computing system, Cache logic purges storage addresses from the cache, based on the command, to the higher level memory.

公开(公告)号：US10437729B2

公开(公告)日：2019-10-08

申请号：US15491149

申请日：2017-04-19

Applicant: International Business Machines Corporation

Inventor： Ekaterina M. Ambroladze ,  Deanna P. D. Berger ,  Michael A. Blake ,  Pak-kin Mak ,  Robert J. Sonnelitter, III ,  Guy G. Tracy ,  Chad G. Wilson

IPC: G06F12/00 ,  G06F13/00 ,  G06F12/0891 ,  G06F12/0804 ,  G06F12/0864 ,  G06F12/0897

Abstract: In an approach for purging an address range from a cache, a processor quiesces a computing system. Cache logic issues a command to purge a section of a cache to higher level memory, wherein the command comprises a starting storage address and a range of storage addresses to be purged. Responsive to each cache of the computing system activating the command, cache logic ends the quiesce of the computing system. Subsequent to ending the quiesce of the computing system, Cache logic purges storage addresses from the cache, based on the command, to the higher level memory.

公开(公告)号：US20190251037A1

公开(公告)日：2019-08-15

申请号：US16403082

申请日：2019-05-03

Applicant: International Business Machines Corporation

Inventor： Ekaterina M. Ambroladze ,  Deanna P. D. Berger ,  Michael A. Blake ,  Pak-kin Mak ,  Robert J. Sonnelitter, III ,  Guy G. Tracy ,  Chad G. Wilson

IPC: G06F12/0891 ,  G06F12/0897 ,  G06F12/0804 ,  G06F12/0864

CPC classification number: G06F12/0891 ,  G06F12/0804 ,  G06F12/0864 ,  G06F12/0897 ,  G06F2212/1024 ,  G06F2212/60

Abstract: In an approach for purging an address range from a cache, a processor quiesces a computing system. Cache logic issues a command to purge a section of a cache to higher level memory, wherein the command comprises a starting storage address and a range of storage addresses to be purged. Responsive to each cache of the computing system activating the command, cache logic ends the quiesce of the computing system. Subsequent to ending the quiesce of the computing system, Cache logic purges storage addresses from the cache, based on the command, to the higher level memory.

公开(公告)号：US20190251036A1

公开(公告)日：2019-08-15

申请号：US16402996

申请日：2019-05-03

Applicant: International Business Machines Corporation

Inventor： Ekaterina M. Ambroladze ,  Deanna P. D. Berger ,  Michael A. Blake ,  Pak-kin Mak ,  Robert J. Sonnelitter, III ,  Guy G. Tracy ,  Chad G. Wilson

IPC: G06F12/0891 ,  G06F12/0897 ,  G06F12/0804 ,  G06F12/0864

CPC classification number: G06F12/0891 ,  G06F12/0804 ,  G06F12/0864 ,  G06F12/0897 ,  G06F2212/1024 ,  G06F2212/60

Abstract: In an approach for purging an address range from a cache, a processor quiesces a computing system. Cache logic issues a command to purge a section of a cache to higher level memory, wherein the command comprises a starting storage address and a range of storage addresses to be purged. Responsive to each cache of the computing system activating the command, cache logic ends the quiesce of the computing system. Subsequent to ending the quiesce of the computing system, Cache logic purges storage addresses from the cache, based on the command, to the higher level memory.

公开(公告)号：US20180307612A1

公开(公告)日：2018-10-25

申请号：US15491149

申请日：2017-04-19

Applicant: International Business Machines Corporation

Inventor： Ekaterina M. Ambroladze ,  Deanna P. D. Berger ,  Michael A. Blake ,  Pak-kin Mak ,  Robert J. Sonnelitter, III ,  Guy G. Tracy ,  Chad G. Wilson

IPC: G06F12/0891 ,  G06F12/0804

CPC classification number: G06F12/0891 ,  G06F12/0804 ,  G06F12/0864 ,  G06F12/0897 ,  G06F2212/1024 ,  G06F2212/60

Abstract: In an approach for purging an address range from a cache, a processor quiesces a computing system. Cache logic issues a command to purge a section of a cache to higher level memory, wherein the command comprises a starting storage address and a range of storage addresses to be purged. Responsive to each cache of the computing system activating the command, cache logic ends the quiesce of the computing system. Subsequent to ending the quiesce of the computing system, Cache logic purges storage addresses from the cache, based on the command, to the higher level memory.

公开(公告)号：US09507660B2

公开(公告)日：2016-11-29

申请号：US15097531

申请日：2016-04-13

Applicant: International Business Machines Corporation

Inventor： Ekaterina M. Ambroladze ,  Michael A. Blake ,  Michael Fee ,  Arthur J. O'Neill, Jr.

IPC: G06F11/00 ,  G06F11/07 ,  G06F12/08

CPC classification number: G06F11/3037 ,  G06F11/073 ,  G06F11/0754 ,  G06F11/076 ,  G06F11/079 ,  G06F11/0793 ,  G06F11/08 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0897 ,  G06F12/128 ,  G06F2201/85 ,  G06F2201/885 ,  G06F2212/1032 ,  G06F2212/281 ,  G06F2212/283 ,  G06F2212/601 ,  G06F2212/608 ,  G06F2212/69

Abstract: In an approach for taking corrupt portions of cache offline during runtime, a notification of a section of a cache to be taken offline is received, wherein the section includes one or more sets in one or more indexes of the cache. An indication is associated with each set of the one or more sets in a first index of the one or more indexes, wherein the indication marks the respective set as unusable for future operations. Data is purged from the one or more sets in the first index of the cache. Each set of the one or more sets in the first index is marked as invalid.

Abstract translation: 在用于在运行时间内使缓存脱机的损坏部分的方法中，接收要脱机的高速缓存的一部分的通知，其中所述部分包括高速缓存的一个或多个索引中的一个或多个集合。 指示与一个或多个索引的第一索引中的一个或多个集合的每个集合相关联，其中该指示将相应集合标记为不可用于将来的操作。 从缓存的第一个索引中的一个或多个集合中清除数据。 第一个索引中的一个或多个集合的每个集合被标记为无效。

公开(公告)号：US20130042144A1

公开(公告)日：2013-02-14

申请号：US13655088

申请日：2012-10-18

Applicant: International Business Machines Corporation

Inventor： Michael A. Blake ,  Timothy C. Bronson ,  Hieu T. Huynh ,  Pak-kin Mak

IPC: G06F11/26 ,  G06F11/27

CPC classification number: G11C29/08 ,  G06F11/1666 ,  G06F11/20 ,  G11C11/401 ,  G11C29/883 ,  G11C2029/0401

Abstract: A computer implemented method of embedded dynamic random access memory (EDRAM) macro disablement. The method includes isolating an EDRAM macro of a cache memory bank, the cache memory bank being divided into at least three rows of a plurality of EDRAM macros, the EDRAM macro being associated with one of the at least three rows. Each line of the EDRAM macro is iteratively tested, the testing including attempting at least one write operation at each line of the EDRAM macro. It is determined that an error occurred during the testing. Write perations for an entire row of EDRAM macros associated with the EDRAM macro are disabled based on the determining.

Abstract translation: 嵌入式动态随机存取存储器（EDRAM）宏禁用的计算机实现方法。 该方法包括隔离高速缓存存储体的EDRAM宏，该高速缓存存储体被划分成多个EDRAM宏的至少三行，该EDRAM宏与至少三行之一相关联。 EDRAM宏的每一行被迭代测试，测试包括尝试在EDRAM宏的每一行进行至少一次写入操作。 确定在测试期间发生错误。 基于确定，禁用与EDRAM宏相关联的整行EDRAM宏的写入。

公开(公告)号：US20230315633A1

公开(公告)日：2023-10-05

申请号：US17712510

申请日：2022-04-04

Applicant: International Business Machines Corporation

Inventor： Ashraf ElSharif ,  Richard Joseph Branciforte ,  Gregory William Alexander ,  Deanna Postles Dunn Berger ,  Timothy Bronson ,  Aaron Tsai ,  Taylor J. Pritchard ,  Markus Kaltenbach ,  Christian Jacobi ,  Michael A. Blake

IPC: G06F12/0811

CPC classification number: G06F12/0811 ,  G06F2212/62

Abstract: A computer system includes a processor core and a memory system in signal communication with the processor core. The memory system includes a first cache and a second cache. The first cache is arranged at a first level of a hierarchy in the memory system and is configured to store a plurality of first-cache entries. The second cache is arranged at a second level of the hierarchy that is lower than the first level, and stores a plurality of second-cache entries. The first cache maintains a directory that contains information for each of the first-cache entries. The second cache maintains a shadow pointer directory (SPD) that includes one or more SPD entries that maps each of the first-cache entries to a corresponding second cache entry at a lower-level cache location.

公开(公告)号：US10339064B2

公开(公告)日：2019-07-02

申请号：US15472610

申请日：2017-03-29

Applicant: International Business Machines Corporation

Inventor： Michael A. Blake ,  Timothy C. Bronson ,  Jason D. Kohl ,  Pak-Kin Mak ,  Vesselina K. Papazova

IPC: G06F13/18 ,  G06F12/0877

Abstract: Embodiments of the present invention are directed to hot cache line arbitration. An example of a computer-implemented method for hot cache line arbitration includes detecting, by a processing device, a hot cache line scenario. The computer-implemented method further includes tracking, by the processing device, hot cache line requests from requesters to determine subsequent satisfaction of the requests. The computer-implemented method further includes facilitating, by the processing device, servicing of the requests according to hierarchy of the requestors.

公开(公告)号：US10331576B2

公开(公告)日：2019-06-25

申请号：US15496525

申请日：2017-04-25

Applicant: International Business Machines Corporation

Inventor： Michael A. Blake ,  Pak-kin Mak ,  Robert J. Sonnelitter, III ,  Timothy W. Steele ,  Gary E. Strait ,  Poornima P. Sulibele ,  Guy G. Tracy

IPC: G06F12/14 ,  G06F12/0891 ,  G06F13/40

Abstract: A computer implemented method for avoiding false activation of hang avoidance mechanisms of a system is provided. The computer implemented method includes receiving, by a nest of the system, rejects from a processor core of the system. The rejects are issued based on a cache line being locked by the processor core. The computer implemented method includes accumulating the rejects by the nest. The computer implemented method includes determining, by the nest, when an amount of the rejects accumulated by the nest has met or exceeded a programmable threshold. The computer implemented method also includes triggering, by the nest, a global reset to counters of the hang avoidance mechanisms of a system in response to the amount meeting or exceeding the programmable threshold.