公开(公告)号：US20160217077A1

公开(公告)日：2016-07-28

申请号：US14606432

申请日：2015-01-27

Applicant: International Business Machines Corporation

Inventor： Ekaterina M. Ambroladze ,  Timothy C. Bronson ,  Garrett M. Drapala ,  Michael Fee ,  Matthias Klein ,  Pak-kin Mak ,  Robert J. Sonnelitter, III ,  Gary E. Strait

IPC: G06F12/08

CPC classification number: G06F12/0855 ,  G06F12/0833 ,  G06F2212/1021 ,  G06F2212/608 ,  G06F2212/621

Abstract: Maintaining store order with high throughput in a distributed shared memory system. A request is received for a first ordered data store and a coherency check is initiated. A signal is sent that pipelining of a second ordered data store can be initiated. If a delay condition is encountered during the coherency check for the first ordered data store, rejection of the first ordered data store is signaled. If a delay condition is not encountered during the coherency check for the first ordered data store, a signal is sent indicating a readiness to continue pipelining of the second ordered data store.

Abstract translation: 在分布式共享存储器系统中维护具有高吞吐量的存储顺序。 接收到针对第一有序数据存储的请求，并且启动一致性检查。 发送信号，可以启动第二个有序数据存储的流水线。 如果在第一有序数据存储器的一致性检查期间遇到延迟条件，则发信号通知第一有序数据存储器的拒绝。 如果在第一有序数据存储器的一致性检查期间没有遇到延迟条件，则发送指示准备继续流水线化第二有序数据存储的信号。

公开(公告)号：US09348524B1

公开(公告)日：2016-05-24

申请号：US14547639

申请日：2014-11-19

Applicant: International Business Machines Corporation

Inventor： Timothy C. Bronson ,  Garrett M. Drapala ,  Michael F. Fee ,  Pak-Kin Mak ,  Arthur J. O'Neill ,  Robert J. Sonnelitter, III

IPC: G06F3/06 ,  G06F12/08

CPC classification number: G06F12/0802 ,  G06F12/0811 ,  G06F12/0837 ,  G06F12/0842 ,  G06F2212/1016 ,  G06F2212/1048 ,  G06F2212/283

Abstract: A computing device is provided and includes a plurality of nodes. Each node includes multiple chips and a node controller at which the multiple chips are assignable to logical partitions. Each of the multiple chips includes processors and a memory unit configured to handle local memory operations originating from the processors. The node controller includes a dynamic memory relocation (DMR) mechanism configured to move data having a DMR storage increment address relative to a local one of the memory units without interrupting a processing of the data by at least one of the logical partitions. During movement of the data by the DMR mechanism, the memory units are disabled from handling the local memory operations matching the DMR storage increment address and the node controller handles the local memory operations matching the DMR storage increment address.

Abstract translation: 提供了一种计算设备并且包括多个节点。 每个节点包括多个芯片和一个节点控制器，多个芯片可以分配到逻辑分区。 多个芯片中的每一个包括处理器和被配置为处理源自处理器的本地存储器操作的存储器单元。 节点控制器包括动态存储器重定位（DMR）机制，其被配置为移动具有相对于存储器单元中的本地存储器单元的DMR存储增量地址的数据，而不会中断至少一个逻辑分区对数据的处理。 在通过DMR机制移动数据期间，禁止存储器单元处理与DMR存储增量地址匹配的本地存储器操作，并且节点控制器处理与DMR存储器增量地址匹配的本地存储器操作。

公开(公告)号：US09323676B2

公开(公告)日：2016-04-26

申请号：US13784958

申请日：2013-03-05

Applicant: International Business Machines Corporation

Inventor： Timothy C. Bronson ,  Garrett M. Drapala ,  Rebecca M. Gott ,  Pak-Kin Mak ,  Vijayalakshmi Srinivasan ,  Craig R. Walters

IPC: G06F12/08

CPC classification number: G06F12/0833 ,  G06F12/0811 ,  G06F12/0831 ,  G06F2212/283 ,  G06F2212/621

Abstract: Embodiments relate to a non-data inclusive coherent (NIC) directory for a symmetric multiprocessor (SMP) of a computer. An aspect includes determining a first eviction entry of a highest-level cache in a multilevel caching structure of the first processor node of the SMP. Another aspect includes determining that the NIC directory is not full. Another aspect includes determining that the first eviction entry of the highest-level cache is owned by a lower-level cache in the multilevel caching structure. Another aspect includes, based on the NIC directory not being full and based on the first eviction entry of the highest-level cache being owned by the lower-level cache, installing an address of the first eviction entry of the highest-level cache in a first new entry in the NIC directory. Another aspect includes invalidating the first eviction entry in the highest-level cache.

公开(公告)号：US09268660B2

公开(公告)日：2016-02-23

申请号：US14205910

申请日：2014-03-12

Applicant: International Business Machines Corporation

Inventor： Garrett M. Drapala ,  Gary E. Strait

IPC: G06F11/273 ,  G11C29/12 ,  G11C29/40 ,  G11C29/04

CPC classification number: G11C29/04 ,  G06F11/273 ,  G11C29/12 ,  G11C29/40 ,  G11C29/42 ,  G11C29/44 ,  G11C29/52

Abstract: Embodiments relate to matrix and compression-based error detection. An aspect includes summing, by each of a first plurality of summing modules of a first compressor, a respective row of a matrix, the matrix comprising a plurality of rows and a plurality of columns of output bits of a circuit under test wherein each output bit of the circuit under test comprises an element of the matrix, and is a member of a row of a column that is orthogonal to the row. Another aspect includes summing, by each of a second plurality of summing modules of a second compressor, a respective column of output bits of the matrix. Yet another aspect includes determining a presence of an error in the circuit under test based at least one of an output of the first compressor and an output of the second compressor.

公开(公告)号：US09244851B2

公开(公告)日：2016-01-26

申请号：US13746882

申请日：2013-01-22

Applicant: International Business Machines Corporation

Inventor： Ekaterina M. Ambroladze ,  Michael A. Blake ,  Timothy C. Bronson ,  Garrett M. Drapala ,  Pak-kin Mak ,  Arthur J. O'Neill

IPC: G06F12/08

CPC classification number: G06F12/0891 ,  G06F12/0815 ,  G06F12/0859

Abstract: A technique for cache coherency is provided. A cache controller selects a first set from multiple sets in a congruence class based on a cache miss for a first transaction, and places a lock on the entire congruence class in which the lock prevents other transactions from accessing the congruence class. The cache controller designates in a cache directory the first set with a marked bit indicating that the first transaction is working on the first set, and the marked bit for the first set prevents the other transactions from accessing the first set within the congruence class. The cache controller removes the lock on the congruence class based on the marked bit being designated for the first set, and resets the marked bit for the first set to an unmarked bit based on the first transaction completing work on the first set in the congruence class.

公开(公告)号：US09798663B2

公开(公告)日：2017-10-24

申请号：US14846875

申请日：2015-09-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Timothy C. Bronson ,  Garrett M. Drapala ,  Pak-kin Mak ,  Vesselina K. Papazova ,  Hanno Ulrich

IPC: G06F12/0815 ,  G06F12/14 ,  G06F12/0813 ,  G06F12/0831

CPC classification number: G06F12/0815 ,  G06F12/0813 ,  G06F12/0835 ,  G06F12/1416 ,  G06F2212/314 ,  G06F2212/50 ,  G06F2212/621 ,  G06F2212/622

Abstract: A cache coherency management facility to reduce latency in granting exclusive access to a cache in certain situations. A node requests exclusive access to a cache line of the cache. The node is in one region of nodes of a plurality of regions of nodes. The one region of nodes includes the node requesting exclusive access and another node of the computing environment, in which the node and the another node are local to one another as defined by a predetermined criteria. The node requesting exclusive access checks a locality cache coherency state of the another node, the locality cache coherency state being specific to the another node and indicating whether the another node has access to the cache line. Based on the checking indicating that the another node has access to the cache line, a determination is made that the node requesting exclusive access is to be granted exclusive access to the cache line. The determining being independent of transmission of information relating to the cache line from one or more other nodes of the one or more other regions of nodes.

公开(公告)号：US09594689B2

公开(公告)日：2017-03-14

申请号：US14616784

申请日：2015-02-09

Applicant: International Business Machines Corporation

Inventor： Ekaterina M. Ambroladze ,  Deanna P. Berger ,  Garrett M. Drapala ,  Michael Fee ,  Pak-kin Mak ,  Arthur J. O'Neill, Jr. ,  Diana L. Orf

IPC: G06F12/00 ,  G06F12/08 ,  G06F3/06

CPC classification number: G06F12/0868 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0685 ,  G06F11/10 ,  G06F11/1446 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0808 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0897 ,  G06F2212/1016 ,  G06F2212/311 ,  G06F2212/60 ,  G06F2212/608

Abstract: In an approach for backing up designated data located in a cache, data stored within an index of a cache is identified, wherein the data has an associated designation indicating that the data is applicable to be backed up to a higher level memory. It is determined that the data stored to the cache has been updated. A status associated with the data is adjusted, such that the adjusted status indicates that the data stored to the cache has not been changed. A copy of the data is created. The copy of the data is stored to the higher level memory.

Abstract translation: 在用于备份位于高速缓存中的指定数据的方法中，识别存储在高速缓存的索引内的数据，其中数据具有指示该数据可应用于备份到较高级存储器的相关联的指定。 确定存储到高速缓存的数据已被更新。 调整与数据相关联的状态，使得调整状态指示存储到高速缓存的数据未被改变。 创建数据的副本。 数据的副本存储到较高级别的内存。

公开(公告)号：US09459998B2

公开(公告)日：2016-10-04

申请号：US14613800

申请日：2015-02-04

Applicant: International Business Machines Corporation

Inventor： Michael A. Blake ,  Garrett M. Drapala ,  James F. Driftmyer ,  Deanna P. Berger ,  Pak-kin Mak ,  Timothy J. Slegel ,  Rebecca S. Wisniewski

IPC: G06F12/08 ,  G06F12/02

CPC classification number: G06F12/02 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0848 ,  G06F12/0884 ,  G06F12/0897 ,  G06F2212/282 ,  G06F2212/283

Abstract: A multi-boundary address protection range is provided to prevent key operations from interfering with a data move performed by a dynamic memory relocation (DMR) move operation. Any key operation address that is within the move boundary address range gets rejected back to the hypervisor. Further, logic exists across a set of parallel slices to synchronize the DMR move operation as it crosses a protected boundary address range.

Abstract translation: 提供多边界地址保护范围以防止键操作干扰由动态存储器重定位（DMR）移动操作执行的数据移动。 移动边界地址范围内的任何键操作地址将被拒绝回管理程序。 此外，跨越一组并行片段存在逻辑，以在DMR移动操作跨越受保护的边界地址范围时同步DMR移动操作。

公开(公告)号：US20160239450A1

公开(公告)日：2016-08-18

申请号：US14621467

申请日：2015-02-13

Applicant: International Business Machines Corporation

Inventor： Garrett M. Drapala ,  Michael F. Fee ,  Kenneth D. Klapproth ,  Robert J. Sonnelitter, III

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4068 ,  G06F13/4221

Abstract: In one embodiment, a computer-implemented method includes instructing two or more processors that are operating in a normal state of a symmetric multiprocessing (SMP) network to transition from the normal state to a slow state. The two or more processors reduce their frequencies to respective target frequencies in a transitional state when transitioning from the normal state to the slow state. It is determined that the two or more processors have achieved their respective target frequencies for the slow state. The slow state is entered, responsive to this determination. Responsive to entering the slow state, a first processor of the two or more processors is instructed to send empty packets across an interconnect to compensate for a first greatest potential rate differential between the first processor and a remainder of the two or more processors during the slow state.

Abstract translation: 在一个实施例中，计算机实现的方法包括指示在对称多处理（SMP）网络的正常状态下操作的两个或更多个处理器从正常状态转换到慢速状态。 当从正常状态转换到慢速状态时，两个或多个处理器将它们的频率降低到处于过渡状态的各个目标频率。 确定两个或更多个处理器已经实现了其缓慢状态的各自的目标频率。 响应此确定，输入缓慢状态。 响应于进入缓慢状态，指示两个或多个处理器的第一处理器通过互连发送空分组以补偿在慢速期间第一处理器与两个或多个处理器的剩余部分之间的第一最大潜在速率差 州。

公开(公告)号：US20160110287A1

公开(公告)日：2016-04-21

申请号：US14518428

申请日：2014-10-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Timothy C. Bronson ,  Garrett M. Drapala ,  Pak-kin Mak ,  Vesselina K. Papazova ,  Hanno Ulrich

IPC: G06F12/08 ,  G06F12/14

CPC classification number: G06F12/0815 ,  G06F12/0813 ,  G06F12/0835 ,  G06F12/1416 ,  G06F2212/314 ,  G06F2212/50 ,  G06F2212/621 ,  G06F2212/622

Abstract: A cache coherency management facility to reduce latency in granting exclusive access to a cache in certain situations. A node requests exclusive access to a cache line of the cache. The node is in one region of nodes of a plurality of regions of nodes. The one region of nodes includes the node requesting exclusive access and another node of the computing environment, in which the node and the another node are local to one another as defined by a predetermined criteria. The node requesting exclusive access checks a locality cache coherency state of the another node, the locality cache coherency state being specific to the another node and indicating whether the another node has access to the cache line. Based on the checking indicating that the another node has access to the cache line, a determination is made that the node requesting exclusive access is to be granted exclusive access to the cache line. The determining being independent of transmission of information relating to the cache line from one or more other nodes of the one or more other regions of nodes.

Abstract translation: 高速缓存一致性管理工具，可在某些情况下减少授予对高速缓存的独占访问的延迟。 节点请求对缓存的高速缓存行的独占访问。 节点在节点的多个区域的节点的一个区域中。 节点的一个区域包括请求独占访问的节点和计算环境的另一个节点，其中节点和另一个节点是按照预定标准定义的彼此本地的。 请求独占访问的节点检查另一个节点的局部高速缓存一致性状态，该位置高速缓存一致性状态是另一个节点特有的，并指示另一个节点是否可以访问高速缓存行。 基于指示另一节点能够访问高速缓存行的检查，确定请求独占访问的节点被授予对高速缓存行的独占访问。 该确定独立于与一个或多个其他节点区域的一个或多个其他节点相关的与高速缓存线有关的信息的传输。