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11.发明授权III-V compound semiconductor material passivation with crystalline interlayer 有权III-V化合物半导体材料钝化与晶体中间层公开(公告)号：US08809860B2
公开(公告)日：2014-08-19
申请号：US13775968
申请日：2013-02-25
CPC分类号： H01L29/0603 , H01L21/28158 , H01L21/28264 , H01L29/517 , H01L29/66522 , H01L29/78 , H01L29/7833
摘要： The present disclosure reduces and, in some instances, eliminates the density of interface states in III-V compound semiconductor materials by providing a thin crystalline interlayer onto an upper surface of a single crystal III-V compound semiconductor material layer to protect the crystallinity of the single crystal III-V compound semiconductor material layer's surface atoms prior to further processing of the structure.
摘要翻译： 本公开通过在单晶III-V化合物半导体材料层的上表面上提供薄的晶体中间层来减少并且在一些情况下消除III-V族化合物半导体材料中的界面态的密度，以保护单晶III-V化合物半导体材料层的结晶度 单晶III-V化合物半导体材料层的表面原子在进一步处理结构之前。
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公开(公告)号：US20140185981A1
公开(公告)日：2014-07-03
申请号：US13732494
申请日：2013-01-02
CPC分类号： H01L33/52 , G06F17/5068 , H01L27/14
摘要： A method of forming an integrated photonic semiconductor structure having a photonic device and adjacent CMOS devices may include depositing a first silicon nitride layer over the adjacent CMOS devices and depositing an oxide layer over the first silicon nitride layer, wherein the oxide layer conformally covers the first silicon nitride layer and the underlying adjacent CMOS devices to form a substantially planarized surface over the adjacent CMOS devices. A second silicon nitride layer is then deposited over the oxide layer and a region corresponding to forming the photonic device. A germanium layer is deposited over the oxide layer and the region corresponding to forming the photonic device. The germanium layer deposited over the adjacent CMOS devices is etched to form a germanium active layer within the photonic region, whereby the oxide layer and the second silicon nitride layer protect the adjacent CMOS devices during the etching of the germanium.
摘要翻译： 形成具有光子器件和相邻CMOS器件的集成光子半导体结构的方法可以包括在相邻的CMOS器件上沉积第一氮化硅层并在第一氮化硅层上沉积氧化物层，其中氧化物层保形地覆盖第一 氮化硅层和下面的相邻CMOS器件，以在相邻的CMOS器件上形成基本平坦化的表面。 然后在氧化物层上沉积第二氮化硅层和对应于形成光子器件的区域。 在氧化物层和对应于形成光子器件的区域上沉积锗层。 蚀刻沉积在相邻CMOS器件上的锗层，以在光子区域内形成锗有源层，由此在蚀刻锗期间，氧化物层和第二氮化硅层保护相邻的CMOS器件。
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13.发明申请III-V COMPOUND SEMICONDUCTOR MATERIAL PASSIVATION WITH CRYSTALLINE INTERLAYER 有权III-V化合物半导体材料与晶体间隔层的钝化公开(公告)号：US20130168834A1
公开(公告)日：2013-07-04
申请号：US13775968
申请日：2013-02-25
IPC分类号： H01L29/06
CPC分类号： H01L29/0603 , H01L21/28158 , H01L21/28264 , H01L29/517 , H01L29/66522 , H01L29/78 , H01L29/7833
摘要： The present disclosure reduces and, in some instances, eliminates the density of interface states in III-V compound semiconductor materials by providing a thin crystalline interlayer onto an upper surface of a single crystal III-V compound semiconductor material layer to protect the crystallinity of the single crystal III-V compound semiconductor material layer's surface atoms prior to further processing of the structure.
摘要翻译： 本公开通过在单晶III-V化合物半导体材料层的上表面上提供薄的晶体中间层来减少并且在一些情况下消除III-V族化合物半导体材料中的界面态的密度，以保护单晶III-V化合物半导体材料层的结晶度 单晶III-V化合物半导体材料层的表面原子在进一步处理结构之前。
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公开(公告)号：US09658400B2
公开(公告)日：2017-05-23
申请号：US14831383
申请日：2015-08-20
CPC分类号： G02B6/132 , G02B6/1228 , G02B6/136
摘要： A method of forming a device for propagating light includes providing a substrate having a semiconductor material; placing an insulating layer on the substrate; providing a recess reaching through the insulating layer and into the substrate; filling the recess at least partially with a filler material; and arranging a waveguide in or on the filler material.
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公开(公告)号：US20160172465A1
公开(公告)日：2016-06-16
申请号：US15047871
申请日：2016-02-19
发明人： Cheng-Wei Cheng , Edward W. Kiewra , Amlan Majumdar , Uzma Rana , Devendra K. Sadana , Kuen-Ting Shiu , Yanning Sun
IPC分类号： H01L29/66 , H01L29/201 , H01L29/20 , H01L21/762 , H01L29/06
CPC分类号： H01L29/66522 , H01L21/02488 , H01L21/02494 , H01L21/02538 , H01L21/0262 , H01L21/02639 , H01L21/76283 , H01L29/0649 , H01L29/20 , H01L29/2003 , H01L29/201 , H01L29/66742 , H01L29/78603 , H01L29/78681
摘要： A method of forming a semiconductor substrate including a type III-V semiconductor material directly on a dielectric material that includes forming a trench in a dielectric layer, and forming a via within the trench extending from a base of the trench to an exposed upper surface of an underlying semiconductor including substrate. A III-V semiconductor material is formed extending from the exposed upper surface of the semiconductor substrate filling at least a portion of the trench.
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公开(公告)号：US09304335B2
公开(公告)日：2016-04-05
申请号：US14332886
申请日：2014-07-16
发明人： John J. Ellis-Monaghan , William M. Green , Michael J. Hauser , Edward W. Kiewra , Xuefeng Liu , Steven M. Shank
IPC分类号： H01L21/782 , H01L27/14 , H01L29/78 , G02F1/025 , H01L29/10 , H01L29/08 , H01L29/423 , H01L29/40 , H01L29/06 , H01L29/49 , H01L27/088 , H01L21/306 , H01L29/66 , H01L27/06 , G02B6/136 , G02B6/12
CPC分类号： G02F1/025 , G02B6/136 , G02B2006/12061 , G02B2006/12142 , G02B2006/12176 , H01L21/30604 , H01L27/0617 , H01L27/088 , H01L29/0634 , H01L29/0653 , H01L29/0696 , H01L29/0865 , H01L29/0882 , H01L29/1095 , H01L29/402 , H01L29/42356 , H01L29/4916 , H01L29/66681 , H01L29/66689 , H01L29/7823 , H01L29/7824 , H01L29/78624
摘要： A device includes a laterally diffused metal-oxide-semiconductor (LDMOS) device integrated with an optical modulator. An optical waveguide of the optical modulator includes a silicon-containing structure in a drift region of the LDMOS device.
摘要翻译： 一种器件包括与光学调制器集成的横向扩散的金属氧化物半导体（LDMOS）器件。 光调制器的光波导包括在LDMOS器件的漂移区域中的含硅结构。
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公开(公告)号：US09287115B2
公开(公告)日：2016-03-15
申请号：US14206220
申请日：2014-03-12
发明人： Cheng-Wei Cheng , Edward W. Kiewra , Amlan Majumdar , Uzma Rana , Devendra K. Sadana , Kuen-Ting Shiu , Yanning Sun
IPC分类号： H01L21/02
CPC分类号： H01L29/66522 , H01L21/02488 , H01L21/02494 , H01L21/02538 , H01L21/0262 , H01L21/02639 , H01L21/76283 , H01L29/0649 , H01L29/20 , H01L29/2003 , H01L29/201 , H01L29/66742 , H01L29/78603 , H01L29/78681
摘要： A method of forming a semiconductor substrate including a type III-V semiconductor material directly on a dielectric material that includes forming a trench in a dielectric layer, and forming a via within the trench extending from a base of the trench to an exposed upper surface of an underlying semiconductor including substrate. A III-V semiconductor material is formed extending from the exposed upper surface of the semiconductor substrate filling at least a portion of the trench.
摘要翻译： 一种在电介质材料上直接形成包括III-V族半导体材料的半导体衬底的方法，该电介质材料包括在电介质层中形成沟槽，并且在从沟槽的基底延伸到沟槽的暴露的上表面 包括衬底的底层半导体。 从半导体衬底的暴露的上表面延伸填充至少一部分沟槽形成III-V半导体材料。
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公开(公告)号：US20150262818A1
公开(公告)日：2015-09-17
申请号：US14206220
申请日：2014-03-12
发明人： Cheng-Wei Cheng , Edward W. Kiewra , Amlan Majumdar , Uzma Rana , Devendra K. Sadana , Kuen-Ting Shiu , Yanning Sun
CPC分类号： H01L29/66522 , H01L21/02488 , H01L21/02494 , H01L21/02538 , H01L21/0262 , H01L21/02639 , H01L21/76283 , H01L29/0649 , H01L29/20 , H01L29/2003 , H01L29/201 , H01L29/66742 , H01L29/78603 , H01L29/78681
摘要： A method of forming a semiconductor substrate including a type III-V semiconductor material directly on a dielectric material that includes forming a trench in a dielectric layer, and forming a via within the trench extending from a base of the trench to an exposed upper surface of an underlying semiconductor including substrate. A III-V semiconductor material is formed extending from the exposed upper surface of the semiconductor substrate filling at least a portion of the trench.
摘要翻译： 一种在电介质材料上直接形成包括III-V族半导体材料的半导体衬底的方法，该电介质材料包括在电介质层中形成沟槽，并且在从沟槽的基底延伸到沟槽的暴露的上表面 包括衬底的底层半导体。 从半导体衬底的暴露的上表面延伸填充至少一部分沟槽形成III-V半导体材料。
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公开(公告)号：US09136303B2
公开(公告)日：2015-09-15
申请号：US13970754
申请日：2013-08-20
IPC分类号： H01L27/146 , H01L27/144
CPC分类号： H01L27/14607 , H01L27/1443 , H01L27/14625 , H01L27/1463 , H01L27/14643 , H01L27/14689 , H01L31/028
摘要： A method of protecting a CMOS device within an integrated photonic semiconductor structure is provided. The method may include depositing a conformal layer of germanium over the CMOS device and an adjacent area to the CMOS device, depositing a conformal layer of dielectric hardmask over the germanium, and forming, using a mask level, a patterned layer of photoresist for covering the CMOS device and a photonic device formation region within the adjacent area. Openings are etched into areas of the deposited layer of silicon nitride not covered by the patterned photoresist, such that the areas are adjacent to the photonic device formation region. The germanium material is then etched from the conformal layer of germanium at a location underlying the etched openings for forming the photonic device at the photonic device formation region. The conformal layer of germanium deposited over the CMOS device protects the CMOS device.
摘要翻译： 提供了保护集成光子半导体结构内的CMOS器件的方法。 该方法可以包括在CMOS器件上沉积锗的保形层和与CMOS器件相邻的区域，在锗上沉积介电硬掩模的保形层，以及使用掩模级形成图案化的光致抗蚀剂层，以覆盖 CMOS器件和相邻区域内的光子器件形成区域。 将开口蚀刻到未被图案化光致抗蚀剂覆盖的氮化硅的沉积层的区域中，使得该区域与光子器件形成区域相邻。 然后在锗的共形层上蚀刻锗材料，其位于蚀刻开口下方的位置处，以在光子器件形成区域处形成光子器件。 沉积在CMOS器件上的锗的保形层保护CMOS器件。
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公开(公告)号：US20150054041A1
公开(公告)日：2015-02-26
申请号：US13970754
申请日：2013-08-20
IPC分类号： H01L27/146
CPC分类号： H01L27/14607 , H01L27/1443 , H01L27/14625 , H01L27/1463 , H01L27/14643 , H01L27/14689 , H01L31/028
摘要： A method of protecting a CMOS device within an integrated photonic semiconductor structure is provided. The method may include depositing a conformal layer of germanium over the CMOS device and an adjacent area to the CMOS device, depositing a conformal layer of dielectric hardmask over the germanium, and forming, using a mask level, a patterned layer of photoresist for covering the CMOS device and a photonic device formation region within the adjacent area. Openings are etched into areas of the deposited layer of silicon nitride not covered by the patterned photoresist, such that the areas are adjacent to the photonic device formation region. The germanium material is then etched from the conformal layer of germanium at a location underlying the etched openings for forming the photonic device at the photonic device formation region. The conformal layer of germanium deposited over the CMOS device protects the CMOS device.
摘要翻译： 提供了保护集成光子半导体结构内的CMOS器件的方法。 该方法可以包括在CMOS器件上沉积锗的保形层和与CMOS器件相邻的区域，在锗上沉积介电硬掩模的保形层，以及使用掩模级形成图案化的光致抗蚀剂层，以覆盖 CMOS器件和相邻区域内的光子器件形成区域。 将开口蚀刻到未被图案化光致抗蚀剂覆盖的氮化硅的沉积层的区域中，使得该区域与光子器件形成区域相邻。 然后在锗的共形层上蚀刻锗材料，其位于蚀刻开口下方的位置处，以在光子器件形成区域处形成光子器件。 沉积在CMOS器件上的锗的保形层保护CMOS器件。
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