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    RAPID MELT GROWTH PHOTODETECTOR
    1.
    发明申请
    RAPID MELT GROWTH PHOTODETECTOR 审中-公开

    公开(公告)号：US20180301568A1

    公开(公告)日：2018-10-18

    申请号：US15486810

    申请日：2017-04-13

    申请人： International Business Machines Corporation

    发明人： John J. Ellis-Monaghan ,  Edward W. Kiewra ,  Jason S. Orcutt

    IPC分类号： H01L31/0232 ,  G02B6/42

    摘要： Photodetector including: a waveguide of a waveguide material extending over a substrate; an insulating layer formed over the waveguide and having an opening exposing the waveguide; a photodetector layer formed over the insulating layer and into the opening so as to make contact with the waveguide, the photodetector layer having a first end at the opening and a second end distal from the opening, the photodetector layer being a gradient material of the waveguide material and germanium wherein a waveguide material portion of the gradient material varies from a maximum at the first end to a minimum at the second end and wherein a germanium portion of the gradient material varies from a minimum at the first end to a maximum at the second end; a photodetector region at the second end; and a photodetector layer extension extending at an angle from the photodetector layer at the second end.

    Rapid melt growth photodetector
    5.
    发明授权
    Rapid melt growth photodetector 有权

    公开(公告)号：US10103280B1

    公开(公告)日：2018-10-16

    申请号：US15486810

    申请日：2017-04-13

    申请人： International Business Machines Corporation

    发明人： John J. Ellis-Monaghan ,  Edward W. Kiewra ,  Jason S. Orcutt

    IPC分类号： H01L31/02 ,  H01L31/0232 ,  G02B6/42 ,  G02B6/12

    摘要： Photodetector including: a waveguide of a waveguide material extending over a substrate; an insulating layer formed over the waveguide and having an opening exposing the waveguide; a photodetector layer formed over the insulating layer and into the opening so as to make contact with the waveguide, the photodetector layer having a first end at the opening and a second end distal from the opening, the photodetector layer being a gradient material of the waveguide material and germanium wherein a waveguide material portion of the gradient material varies from a maximum at the first end to a minimum at the second end and wherein a germanium portion of the gradient material varies from a minimum at the first end to a maximum at the second end; a photodetector region at the second end; and a photodetector layer extension extending at an angle from the photodetector layer at the second end.

    Electrical coupling of memory cell access devices to a word line
    6.
    发明授权
    Electrical coupling of memory cell access devices to a word line 有权
    存储单元访问设备与字线的电耦合

    公开(公告)号：US09343545B2

    公开(公告)日：2016-05-17

    申请号：US13786573

    申请日：2013-03-06

    申请人： International Business Machines Corporation

    发明人： Chung H. Lam ,  Jing Li ,  Edward W. Kiewra

    IPC分类号： H01L27/118 ,  H01L29/66 ,  H01L27/22 ,  H01L27/24 ,  G11C13/00

    CPC分类号： H01L29/66666 ,  G11C13/003 ,  G11C2213/79 ,  H01L27/228 ,  H01L27/2454 ,  H01L27/2463

    摘要： A memory array and a method for electrically coupling memory cell access devices to a word line. The memory array includes a source line electrically coupled to each source terminal of the memory cell access devices. The memory array also includes a first set of at least two vertical pillars positioned above and electrically coupled to the source line. A second set of vertical pillars electrically isolated from the source line and positioned such that the source line does not extend below the second set of vertical pillars is also included. Furthermore, gate terminals of the memory cell access devices laterally surround the first set of vertical pillars and the second set of vertical pillars. Finally, a first word line contact is positioned between two of the second set of vertical pillars. The first word line contact is electrically coupled to the gate terminals.

    摘要翻译： 一种用于将存储器单元访问设备电耦合到字线的存储器阵列和方法。 存储器阵列包括电耦合到存储器单元访问设备的每个源端的源极线。 存储器阵列还包括位于上方并电耦合到源极线的至少两个垂直柱的第一组。 第二组垂直柱与源极线电隔离并且定位成使得源极线不延伸到第二组垂直柱之下。 此外，存储器单元访问装置的栅极端子横向围绕第一组垂直支柱和第二组垂直支柱。 最后，第一个字线触点位于第二组垂直支柱之间。 第一字线触点电耦合到栅极端子。

    Intergrating a silicon photonics photodetector with CMOS devices
    8.
    发明授权
    Intergrating a silicon photonics photodetector with CMOS devices 有权
    将硅光子学光电探测器与CMOS器件集成在一起

    公开(公告)号：US09036959B2

    公开(公告)日：2015-05-19

    申请号：US13732494

    申请日：2013-01-02

    申请人： International Business Machines Corporation

    发明人： Solomon Assefa ,  Marwan H. Khater ,  Edward W. Kiewra ,  Steven M. Shank

    IPC分类号： G02B6/136 ,  H01L33/52 ,  G06F17/50 ,  H01L27/14

    CPC分类号： H01L33/52 ,  G06F17/5068 ,  H01L27/14

    摘要： A method of forming an integrated photonic semiconductor structure having a photonic device and adjacent CMOS devices may include depositing a first silicon nitride layer over the adjacent CMOS devices and depositing an oxide layer over the first silicon nitride layer, wherein the oxide layer conformally covers the first silicon nitride layer and the underlying adjacent CMOS devices to form a substantially planarized surface over the adjacent CMOS devices. A second silicon nitride layer is then deposited over the oxide layer and a region corresponding to forming the photonic device. A germanium layer is deposited over the oxide layer and the region corresponding to forming the photonic device. The germanium layer deposited over the adjacent CMOS devices is etched to form a germanium active layer within the photonic region, whereby the oxide layer and the second silicon nitride layer protect the adjacent CMOS devices during the etching of the germanium.

    摘要翻译： 形成具有光子器件和相邻CMOS器件的集成光子半导体结构的方法可以包括在相邻的CMOS器件上沉积第一氮化硅层并在第一氮化硅层上沉积氧化物层，其中氧化物层保形地覆盖第一 氮化硅层和下面的相邻CMOS器件，以在相邻的CMOS器件上形成基本平坦化的表面。 然后在氧化物层上沉积第二氮化硅层和对应于形成光子器件的区域。 在氧化物层和对应于形成光子器件的区域上沉积锗层。 蚀刻沉积在相邻CMOS器件上的锗层，以在光子区域内形成锗有源层，由此在蚀刻锗期间，氧化物层和第二氮化硅层保护相邻的CMOS器件。

    ELECTRICAL COUPLING OF MEMORY CELL ACCESS DEVICES TO A WORD LINE
    9.
    发明申请
    ELECTRICAL COUPLING OF MEMORY CELL ACCESS DEVICES TO A WORD LINE 有权

    公开(公告)号：US20140256100A1

    公开(公告)日：2014-09-11

    申请号：US14036447

    申请日：2013-09-25

    申请人： International Business Machines Corporation

    发明人： Chung H. Lam ,  Jing Li ,  Edward W. Kiewra

    IPC分类号： H01L29/66 ,  H01L27/105

    CPC分类号： H01L29/66666 ,  G11C13/003 ,  G11C2213/79 ,  H01L27/228 ,  H01L27/2454 ,  H01L27/2463

    摘要： A memory array and a method for electrically coupling memory cell access devices to a word line. The memory array includes a source line electrically coupled to each source terminal of the memory cell access devices. The memory array also includes a first set of at least two vertical pillars positioned above and electrically coupled to the source line. A second set of vertical pillars electrically isolated from the source line and positioned such that the source line does not extend below the second set of vertical pillars is also included. Furthermore, gate terminals of the memory cell access devices laterally surround the first set of vertical pillars and the second set of vertical pillars. Finally, a first word line contact is positioned between two of the second set of vertical pillars. The first word line contact is electrically coupled to the gate terminals.

    ELECTRICAL COUPLING OF MEMORY CELL ACCESS DEVICES TO A WORD LINE
    10.
    发明申请
    ELECTRICAL COUPLING OF MEMORY CELL ACCESS DEVICES TO A WORD LINE 有权
    将记忆体细胞接入装置的电气耦合到字线

    公开(公告)号：US20140252418A1

    公开(公告)日：2014-09-11

    申请号：US13786573

    申请日：2013-03-06

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Chung H. Lam ,  Jing Li ,  Edward W. Kiewra

    IPC分类号： H01L21/8239 ,  H01L27/105

    CPC分类号： H01L29/66666 ,  G11C13/003 ,  G11C2213/79 ,  H01L27/228 ,  H01L27/2454 ,  H01L27/2463

    摘要： A memory array and a method for electrically coupling memory cell access devices to a word line. The memory array includes a source line electrically coupled to each source terminal of the memory cell access devices. The memory array also includes a first set of at least two vertical pillars positioned above and electrically coupled to the source line. A second set of vertical pillars electrically isolated from the source line and positioned such that the source line does not extend below the second set of vertical pillars is also included. Furthermore, gate terminals of the memory cell access devices laterally surround the first set of vertical pillars and the second set of vertical pillars. Finally, a first word line contact is positioned between two of the second set of vertical pillars. The first word line contact is electrically coupled to the gate terminals.

    摘要翻译： 一种用于将存储器单元访问设备电耦合到字线的存储器阵列和方法。 存储器阵列包括电耦合到存储器单元访问设备的每个源端的源极线。 存储器阵列还包括位于上方并电耦合到源极线的至少两个垂直柱的第一组。 第二组垂直柱与源极线电隔离并且定位成使得源极线不延伸到第二组垂直柱之下。 此外，存储器单元访问装置的栅极端子横向围绕第一组垂直支柱和第二组垂直支柱。 最后，第一个字线触点位于第二组垂直支柱之间。 第一字线触点电耦合到栅极端子。