公开(公告)号：US20090282280A1

公开(公告)日：2009-11-12

申请号：US12379276

申请日：2009-02-18

申请人： Hoe-ju Chung

发明人： Hoe-ju Chung

IPC分类号： G06F1/08

CPC分类号： G11C29/56012

摘要： Provided is a memory system for seamless switching. The memory system includes first through mth chips, where m is a natural number, connected in the form of a daisy chain and configured to transmit at least one of signals and data, a (k−1)th chip of the first through mth chips, where k is a natural number and 2≦k≦m, configured to output a (k−1)th detection signal corresponding to a phase difference between (k−1)th test data of the (k−1)th chip and kth test data of a kth chip of the first through mth chips, and the kth chip including a clock phase control unit configured to control a phase of a received clock signal and to output the phase-controlled clock signal as a kth clock signal, where the clock phase control unit of the kth chip outputs the kth clock signal in response to the (k−1)th detection signal.

摘要翻译： 提供了一种用于无缝切换的存储器系统。 存储器系统包括第一至第m个芯片，其中m是自然数，以菊链的形式连接并被配置为传输信号和数据中的至少一个，第一至第m个芯片的第（k-1）个芯片 ，其中k是自然数，2 <= k <= m，被配置为输出与第（k-1）次的第（k-1）个测试数据之间的相位差相对应的第（k-1） 芯片和第k个测试数据，第k个芯片包括时钟相位控制单元，其被配置为控制接收的时钟信号的相位，并输出相位控制的时钟信号作为第k个时钟信号 ，其中第k个芯片的时钟相位控制单元响应于第（k-1）个检测信号输出第k个时钟信号。

公开(公告)号：US08446988B2

公开(公告)日：2013-05-21

申请号：US13280456

申请日：2011-10-25

申请人： Hoe-ju Chung ,  Jung-bae Lee

发明人： Hoe-ju Chung ,  Jung-bae Lee

IPC分类号： H04L27/06

CPC分类号： H04L25/0264 ,  H04L25/0272

摘要： In a communication system, data is selectively transmitted using single-ended or differential signaling. The data is transmitted in relation to a plurality of clock signals having different relative phases. When the data is transmitted using single-ended signaling, data on adjacent signal lines undergo logic transitions at different times in relation to the plurality of clock signals.

摘要翻译： 在通信系统中，使用单端或差分信令有选择地发送数据。 相对于具有不同相对相位的多个时钟信号发送数据。 当使用单端信令发送数据时，相邻信号线上的数据相对于多个时钟信号在不同时刻进行逻辑转换。

公开(公告)号：US08261004B2

公开(公告)日：2012-09-04

申请号：US13026462

申请日：2011-02-14

申请人： Hoe-ju Chung

发明人： Hoe-ju Chung

IPC分类号： G06F13/00 ,  G06F3/00

CPC分类号： G11C7/1051 ,  G11C5/02 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1069 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2924/15311

摘要： A stacked memory apparatus operating with a compound read buffer is disclosed. The stacked memory apparatus includes an interface device having a main buffer and a plurality of memory devices each having a device read buffer. Systems incorporating one or more stacked memory apparatuses and related method of performing a read operation are also disclosed.

摘要翻译： 公开了一种使用复合读取缓冲器操作的堆叠式存储装置。 堆叠式存储装置包括具有主缓冲器和多个存储装置的接口装置，每个存储装置具有装置读缓冲器。 还公开了包含一个或多个堆叠存储器装置的系统和执行读取操作的相关方法。

公开(公告)号：US07957217B2

公开(公告)日：2011-06-07

申请号：US12266716

申请日：2008-11-07

申请人： Moon-sook Park ,  Hoe-ju Chung ,  Jung-bae Lee

发明人： Moon-sook Park ,  Hoe-ju Chung ,  Jung-bae Lee

IPC分类号： G11C8/00

CPC分类号： G11C5/147 ,  G11C5/04

摘要： The invention relates generally to a multi-chip package (MCP) memory device, and more particularly, but without limitation, to a MCP memory device having a reduced size. In one embodiment, the MCP memory device includes: a transfer memory chip; and a plurality of memory chips coupled to the transfer memory chip, each of the plurality of memory chips including an internal voltage generating circuit, the transfer memory chip configured to receive a plurality of command signals from outside the MCP memory device, the transfer memory chip further configured to output a plurality of control signals to the plurality of memory chips based on the plurality of command signals. Embodiments of the invention also relate to a method of controlling an internal voltage of the MCP memory device.

摘要翻译： 本发明一般涉及一种多芯片封装（MCP）存储器件，尤其涉及但不限于具有减小尺寸的MCP存储器件。 在一个实施例中，MCP存储器件包括：传送存储器芯片; 以及多个存储器芯片，其耦合到所述传送存储器芯片，所述多个存储器芯片中的每一个包括内部电压产生电路，所述传送存储器芯片被配置为从所述MCP存储器设备的外部接收多个命令信号，所述传送存储器芯片 还被配置为基于所述多个命令信号将多个控制信号输出到所述多个存储器芯片。 本发明的实施例还涉及一种控制MCP存储器件的内部电压的方法。

公开(公告)号：US20090319703A1

公开(公告)日：2009-12-24

申请号：US12186040

申请日：2008-08-05

申请人： Hoe-ju Chung

发明人： Hoe-ju Chung

IPC分类号： G06F3/00 ,  G06F12/02 ,  G06F12/06

CPC分类号： G11C7/1051 ,  G11C5/02 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1069 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2924/15311

摘要： A stacked memory apparatus operating with a compound read buffer is disclosed. The stacked memory apparatus includes an interface device having a main buffer and a plurality of memory devices each having a device read buffer. Systems incorporating one or more stacked memory apparatuses and related method of performing a read operation are also disclosed.

摘要翻译： 公开了一种使用复合读取缓冲器操作的堆叠式存储装置。 堆叠式存储装置包括具有主缓冲器和多个存储装置的接口装置，每个存储装置具有装置读缓冲器。 还公开了包含一个或多个堆叠存储器装置的系统和执行读取操作的相关方法。

公开(公告)号：US20090122904A1

公开(公告)日：2009-05-14

申请号：US12230578

申请日：2008-09-02

申请人： Young-chan Jang ,  Hoe-ju Chung

发明人： Young-chan Jang ,  Hoe-ju Chung

IPC分类号： H04L25/49

CPC分类号： H04L25/4917 ,  H04L25/028 ,  H04L25/0292 ,  H04L25/062

摘要： In one embodiment, the apparatus includes a driver circuit configured such that for each symbol in a set of possible symbols, the driver circuit generates at least one data signal at an associated voltage level. Here, adjacent voltage levels defme an associated voltage interval, and the driver circuit is configured to generate the voltage levels such that a central voltage interval is less than at least one of the voltage intervals adjacent to the central voltage interval.

摘要翻译： 在一个实施例中，该装置包括驱动器电路，其被配置为使得对于一组可能符号中的每个符号，驱动器电路在相关联的电压电平产生至少一个数据信号。 这里，相邻电压电平限定相关联的电压间隔，并且驱动器电路被配置为产生电压电平，使得中心电压间隔小于与中心电压间隔相邻的电压间隔中的至少一个。

公开(公告)号：US07463073B2

公开(公告)日：2008-12-09

申请号：US11599212

申请日：2006-11-14

申请人： Hoe-ju Chung ,  Young-chan Jang

发明人： Hoe-ju Chung ,  Young-chan Jang

IPC分类号： H03B1/00

CPC分类号： H03K19/01707 ,  H03K17/6871

摘要： An output driver includes a pull-up unit including a pull-up element and a first inductive peaking element connected in series between a first voltage and an output node and a pull-down unit including a pull-down element and a second inductive peaking element connected in series between a second voltage and the output node. The pull-up and pull-down elements receive an input data signal and adjust a voltage level of the output node, and the first and second inductive peaking elements perform an inductive peaking operation when the input data signal transitions.

摘要翻译： 输出驱动器包括上拉单元，其包括上拉元件和串联连接在第一电压和输出节点之间的第一感应峰值元件和下拉单元，该下拉单元包括下拉元件和第二感应峰值元件 串联连接在第二电压和输出节点之间。 上拉和下拉元件接收输入数据信号并调节输出节点的电压电平，并且当输入数据信号转换时，第一和第二感应峰值元件执行感应峰化操作。

公开(公告)号：US20050240718A1

公开(公告)日：2005-10-27

申请号：US11071586

申请日：2005-03-04

申请人： Hoe-ju Chung ,  Jung-bae Lee

发明人： Hoe-ju Chung ,  Jung-bae Lee

IPC分类号： G11C7/10 ,  G06F12/00 ,  G06F12/14 ,  G06F12/16 ,  G06F13/00 ,  G06F13/42

CPC分类号： G06F13/4243

摘要： Provided is a memory system and a method that can initialize a data channel at a high speed without the need to increase the number of pins in a semiconductor memory device, and not requiring a circuit to perform an initialization. The memory system includes a memory module equipped with a plurality of semiconductor memory devices; a memory controller controlling the semiconductor memory devices; and a data channel and a command/address channel connected between the plurality of semiconductor memory devices and the memory controller, wherein read latencies and write latencies of the plurality of semiconductor memory devices are controlled by the memory controller.

摘要翻译： 提供了一种可以高速初始化数据信道的存储器系统和方法，而不需要增加半导体存储器件中的引脚数量，并且不需要电路来执行初始化。 存储器系统包括配备有多个半导体存储器件的存储器模块; 控制半导体存储器件的存储器控​​制器; 以及连接在所述多个半导体存储器件和所述存储器控制器之间的数据通道和命令/地址通道，其中所述多个半导体存储器件的读取延迟和写入延迟由所述存储器控制器控制。

公开(公告)号：US08223524B2

公开(公告)日：2012-07-17

申请号：US13291340

申请日：2011-11-08

申请人： Hoe-ju Chung

发明人： Hoe-ju Chung

IPC分类号： G11C5/02 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C5/063 ,  G11C5/02 ,  H01L25/0657 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/00014

摘要： A multi-chip package memory includes an interface chip generating at least one reference signal defined in relation to a reference process variation, and a stacked plurality of memory chips electrically connected to the interface chip via a vertical connection path and receiving the reference clock signal via the vertical connection path, wherein each one of the stacked plurality of memory chips is characterized by a process variation and actively compensates for said process variation in relation to the reference signal.

摘要翻译： 多芯片封装存储器包括产生关于参考处理变化定义的至少一个参考信号的接口芯片和经由垂直连接路径电连接到接口芯片的多个存储器芯片，并经由 垂直连接路径，其中堆叠的多个存储器芯片中的每个存储器芯片的特征在于处理变化，并且主动地补偿与参考信号相关的所述处理变化。

公开(公告)号：US08102688B2

公开(公告)日：2012-01-24

申请号：US12367213

申请日：2009-02-06

申请人： Hoe-ju Chung ,  Jung-bae Lee

发明人： Hoe-ju Chung ,  Jung-bae Lee

IPC分类号： G11C5/02

CPC分类号： G11C5/063 ,  G11C5/02 ,  H01L25/18 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device includes a controller, a plurality of substrates, and a plurality of stacked memories that are spaced apart and sequence on each of the substrates. Each of the stacked memories includes an interface chip that is connected to the respective substrate and a plurality of memory chips that are stacked on the interface chip. The controller is configured to control the stacked memories. The interface chips are configured to forward a command signal from the controller through each interface chip in the sequence of stacked memories that is intervening between the controller and a selected stacked memory to which the command signal is directed. The interface chips may forward the command signal from one end of the sequence of the stacked memories on one of the substrates to the selected stacked memory, and forward a response signal from the selected stacked memory through the remaining stacked memories in the sequence on the substrate back to the controller or through the same sequence of stacked memories that was taken by the command signal.

摘要翻译： 半导体存储器件包括控制器，多个衬底以及在每个衬底上间隔开并且顺序的多个堆叠存储器。 每个堆叠的存储器包括连接到相应基板的接口芯片和堆叠在接口芯片上的多个存储器芯片。 控制器被配置为控制堆叠的存储器。 接口芯片被配置为通过介于控制器和命令信号所指向的所选择的堆叠存储器之间的堆叠存储器的顺序中的每个接口芯片从控制器转发命令信号。 接口芯片可以将命令信号从其中一个衬底上的堆叠存储器的序列的一端转发到所选择的堆叠存储器，并且将来自所选择的堆叠存储器的响应信号通过剩余的堆叠存储器按顺序在衬底上转发 返回到控制器或通过命令信号拍摄的相同的堆叠存储器序列。