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11.发明申请公开(公告)号：US20180189643A1
公开(公告)日：2018-07-05
申请号：US15847466
申请日：2017-12-19
Inventor： Chan KIM , Young-Su KWON , Jin Ho HAN
CPC classification number: G06N3/063 , G06K9/00993 , G06K9/4604 , G06K9/4628 , G06K9/6274 , G06K9/66 , G06N3/04 , G06N3/0454 , G06N3/08
Abstract: Provided is an operation method of a convolution circuit. The method includes receiving input feature maps, generating output feature maps corresponding to the respective input feature maps through convolution operations for performing parallel processing with a kernel unit, and outputting the output feature maps to an external memory.
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公开(公告)号：US20170255554A1
公开(公告)日：2017-09-07
申请号：US15241902
申请日：2016-08-19
Inventor： Jin Ho HAN , Young-Su KWON , Kyung Jin BYUN , Nak Woong EUM
IPC: G06F12/0811 , G06F12/0842 , G06F12/0875 , G06F12/084
CPC classification number: G06F12/0811 , G06F12/084 , G06F12/0842 , G06F12/0875 , G06F2212/6042 , G06F2212/62
Abstract: Provided is a cache memory. The cache memory includes a first to Nth level-1 caches configured to correspond to first to Nth cores, respectively, a level-2 sharing cache configured to be shared by the first to Nth level-1 caches, and a coherence controller configured to receive an address from each of the first to Nth cores and allocate at least a partial area in an area of the level-2 sharing cache to one of the first to Nth level-1 caches based on the received address.
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公开(公告)号：US20170255520A1
公开(公告)日：2017-09-07
申请号：US15241808
申请日：2016-08-19
Inventor： Jin Ho HAN , Young-Su KWON , Kyoung Seon SHIN , Kyung Jin BYUN , Nak Woong EUM
IPC: G06F11/10 , G06F12/0895 , G06F12/0804
CPC classification number: G06F11/1076 , G06F12/0804 , G06F12/0808 , G06F12/0864 , G06F12/0895 , G06F12/0897 , G06F2212/1032
Abstract: Provided is an operating method of a cache memory device includes receiving an address from an external device, reading an entry corresponding to at least a portion of the received address among a plurality of entries that are included in the cache memory, performing error detection on additional information that is included in the read entry, and performing a recovery operation on the entry based on a result of error detection and the additional information. The entry includes the additional information and a cache line corresponding to the additional information, and the additional information includes a tag, valid bit, and dirty bit that correspond to the cache line.
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公开(公告)号：US20150293827A1
公开(公告)日：2015-10-15
申请号：US14677297
申请日：2015-04-02
Inventor： Jin-Ho HAN , Young-Su KWON , Kyung-Jin BYUN
IPC: G06F11/263 , G06F11/22
CPC classification number: G06F11/2215
Abstract: The present invention relates to an apparatus for computing an error rate comprising: a first circuit interface being connected to a first sub-circuit receiving data and computing output data through a predetermined computation process; a second circuit interface and being connected to a first test circuit receiving the same data, which is inputted to the first sub-circuit, and computing output data through the predetermined computation process; an error injecting part injecting an error to the first test circuit; an error detecting part comparing output data of the first sub-circuit to output data of the first test circuit; and an error rate computing part computing input node error probability of the first sub-circuit by statistic processing of the compared result. The apparatus and method for computing error rate of the present invention is able to shorten the time required to obtain error probability, compared to the direct simulation of the full circuit.
Abstract translation: 本发明涉及一种用于计算错误率的装置，包括：第一电路接口，连接到第一子电路，接收数据并通过预定的计算过程计算输出数据; 第二电路接口，并连接到接收相同数据的第一测试电路，其被输入到第一子电路，并通过预定的计算过程来计算输出数据; 向第一测试电路注入错误的误差注入部分; 将所述第一子电路的输出数据与所述第一测试电路的输出数据进行比较的误差检测部; 以及错误率计算部分通过对比结果的统计处理来计算第一子电路的输入节点误差概率。 与全电路的直接模拟相比，本发明的计算误差率的装置和方法能够缩短获得误差概率所需的时间。
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15.发明申请PROCESSOR CAPABLE OF DETECTING FAULT AND METHOD OF DETECTING FAULT OF PROCESSOR CORE USING THE SAME 审中-公开检测故障的处理器和使用该处理器核心检测处理器核心的方法公开(公告)号：US20140344619A1
公开(公告)日：2014-11-20
申请号：US14208415
申请日：2014-03-13
Inventor： Young-Su KWON
CPC classification number: G06F11/1641 , G06F9/3851 , G06F9/3869
Abstract: A processor capable of detecting fault and a method of detecting the fault of processor core using the same are disclosed. The processor includes a first processor core, a second processor core, and a fault manager. The first processor core includes one or more pipeline registers. The second processor core has a same structure as the first processor core, and is included in a single chip along with the first processor core. The comparator compares the value of the pipeline register of the first processor core with the value of the pipeline register of the second processor core. The fault manager performs a fault management operation if, as a result of the comparison of the comparator, it is determined that a fault has occurred.
Abstract translation: 公开了一种能够检测故障的处理器和使用该处理器核心检测故障的方法。 处理器包括第一处理器核心，第二处理器核心和故障管理器。 第一个处理器内核包括一个或多个流水线寄存器。 第二处理器核具有与第一处理器核相同的结构，并且与第一处理器核一起被包括在单个芯片中。 比较器将第一处理器核心的流水线寄存器的值与第二处理器核心的流水线寄存器的值进行比较。 如果作为比较器的比较结果，确定发生了故障，则故障管理器执行故障管理操作。
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Patent Agency Ranking
16.发明申请公开(公告)号：US20250158604A1
公开(公告)日：2025-05-15
申请号：US18940129
申请日：2024-11-07
Inventor： Yi-Gyeong KIM , Young-Su KWON , Su-Jin PARK , Young-Deuk JEON , Min-Hyung CHO
Abstract: Disclosed herein is a high-speed I/O circuit for die-to-die interconnect for suppressing an overshoot and an undershoot. A data reception circuit includes a reception circuit configured to convert a reception signal received from an interconnect into a digital signal, a first clipper circuit configured to suppress an overshoot of the reception signal based on current extraction, and a second clipper circuit configured to suppress an undershoot of the reception signal based on current supply.
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公开(公告)号：US20230168936A1
公开(公告)日：2023-06-01
申请号：US17980008
申请日：2022-11-03
Inventor： Jaehoon CHUNG , Young-Su KWON , Jin Ho HAN
IPC: G06F9/50
CPC classification number: G06F9/5027
Abstract: A method and apparatus for allocating tasks through relocating kernel data based on a size of systolic array included in each of the plurality of processors, and relocating input feature map (IFM) data based on a number of the plurality of processors are provided.
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公开(公告)号：US20230069909A1
公开(公告)日：2023-03-09
申请号：US17848855
申请日：2022-06-24
Inventor： Seong Mo PARK , Byounggun CHOI , Bon Tae KOO , Young-Su KWON , Kyung Hwan PARK
IPC: H01L31/02 , G01R31/382
Abstract: Provided herein are a power system based on a beta source and an operating method thereof. The system includes a power generating section including a plurality of beta source-based generators, a power storage section including a plurality of power storages to store electrical energy which is generated from the generators, a multiplexer configured to select at least some of the storages, an optical power learning section to receive electrical signals provided from the storages, and estimate a state of charge (SOC) of each of the storages, through machine learning, an optimal power selecting section to select a power storage, which provides the optimal power, based on the SOC of each of the storages, an output section including a plurality of output devices to output power provided from the storage selected by the optimal power selecting section, and a de-multiplexer to select at least one output device of the output devices.
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公开(公告)号：US20220171708A1
公开(公告)日：2022-06-02
申请号：US17536573
申请日：2021-11-29
Inventor： Joo-Hyun LEE , Young-Su KWON , Jin-Ho HAN
IPC: G06F12/084 , G06F8/41 , G06F8/60
Abstract: Disclosed herein is a heterogeneous system based on unified virtual memory. The heterogeneous system based on unified virtual memory may include a host for compiling a kernel program, which is source code of a user application, in a binary form and delivering the compiled kernel program to a heterogenous system architecture device, the heterogenous system architecture device for processing operation of the kernel program delivered from the host in parallel using two or more different types of processing elements, and unified virtual memory shared between the host and the heterogenous system architecture device.
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20.发明申请公开(公告)号：US20200302279A1
公开(公告)日：2020-09-24
申请号：US16813901
申请日：2020-03-10
Inventor： Hyun Kyu YU , Young-Su KWON , JOO HYUN LEE
Abstract: An electronic device includes first to n-th cells (‘n’ is an integer of 2 or more) that receive spatial-temporal input signals that indicate an event unit in a time window, a summation circuit that sums first to n-th cell signals recorded in the first to n-th cells for each of first to m-th unit times (‘m’ is an integer of 2 or more) dividing the time window to generate first to m-th summation signals, and an encoding circuit that compares each of the first to m-th summation signals with a threshold value to encode the spatial-temporal input signals into a code of the event unit.
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