公开(公告)号：US20160005869A1

公开(公告)日：2016-01-07

申请号：US14416227

申请日：2014-04-16

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Ke WANG ,  Seongyeol YOO ,  Ce NING ,  Wei YANG

IPC: H01L29/786 ,  H01L21/4763 ,  H01L29/51 ,  H01L29/49 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/7869 ,  H01L21/47635 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66969 ,  H01L29/78606

Abstract: Provided are oxide thin-film transistor and display device employing the same, and method for manufacturing an oxide thin-film transistor array substrate. A source electrode and a drain electrode are located below an oxide active layer pattern, and a gate electrode is located below the source electrode and the drain electrode, and the gate insulating layer is located between the gate electrode and the source electrode/the drain electrode.

Abstract translation: 提供了氧化物薄膜晶体管和采用该氧化物薄膜晶体管的显示装置，以及制造氧化物薄膜晶体管阵列基板的方法。 源电极和漏极位于氧化物有源层图案的下方，栅电极位于源极和漏电极的下方，栅极绝缘层位于栅电极和源电极/漏电极之间 。

公开(公告)号：US20250017056A1

公开(公告)日：2025-01-09

申请号：US18892572

申请日：2024-09-23

Applicant: BOE Technology Group Co., Ltd.

Inventor： Dapeng XUE ,  Shuilang DONG ,  Ke WANG ,  Zhanfeng CAO

IPC: H10K59/124 ,  H01L25/075 ,  H01L25/16 ,  H01L33/44 ,  H10K50/858 ,  H10K59/80 ,  H10K71/00

Abstract: A display substrate is provided, which includes a base substrate and a plurality of sub-pixels disposed on the base substrate. At least one sub-pixel includes a light transmittance region and a display region. The display region includes a circuit structure layer and a light-emitting element which are disposed on a base substrate, and the light-emitting element is connected with the circuit structure layer. The display substrate further includes a plurality of insulating layers disposed on the base substrate, and at least one insulating layer is hollowed in the light transmittance region.

公开(公告)号：US20240244747A1

公开(公告)日：2024-07-18

申请号：US17927576

申请日：2021-12-31

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Nianqi YAO ,  Feifei LI ,  Ce NING ,  Zhengliang LI ,  Hehe HU ,  Jiayu HE ,  Jie HUANG ,  Kun ZHAO ,  Zhanfeng CAO ,  Ke WANG

IPC: H05K1/11 ,  H01L23/498 ,  H01L33/62 ,  H05K1/09 ,  H05K1/18

CPC classification number: H05K1/111 ,  H01L23/49838 ,  H01L33/62 ,  H05K1/09 ,  H05K1/181 ,  H05K2201/0338 ,  H05K2201/10106 ,  H05K2201/10151

Abstract: A wiring board includes a base substrate and first connection pads disposed on the base substrate. The first connection pads each include electrical connection layer(s); each electrical connection layer includes a main material layer and protective layer(s) disposed on a side of the main material layer away from the base substrate; the protective layer(s) include a first reference protective layer, which is a protective layer farthest away from the base substrate in the protective layer(s); and a material of the main material layer includes copper. The electrical connection layer(s) includes a first electrical connection layer, which is an electrical connection layer farthest away from the base substrate in the electrical connection layer(s); and in protective layer(s) in the first electrical connection layer, at least a material of the first reference protective layer is capable of forming a first intermetallic compound with a first solder.

公开(公告)号：US20230060979A1

公开(公告)日：2023-03-02

申请号：US17800236

申请日：2021-05-14

Applicant: BOE Technology Group Co., Ltd.

Inventor： Zhiwei LIANG ,  Zhanfeng CAO ,  Ke WANG ,  Yingwei LIU ,  Shunyu YAO ,  Shuang LIANG ,  Muxin DI

IPC: H01L33/62 ,  H01L33/00 ,  H01L33/38 ,  G09G3/32

Abstract: A method for manufacturing an array substrate and an array substrate are provided. The method includes: providing a base substrate; forming a driving circuit layer at a side of the base substrate; and forming a functional device layer at a side of the driving circuit layer. Forming the driving circuit layer includes forming at least one first lead layer. Forming the first lead layer includes: forming a conductive seed layer at the side of the base substrate; forming a removable pattern-defining layer on a surface of the conductive seed layer, the removable pattern-defining layer being provided with a lead opening exposing a part of the conductive seed layer; forming, in the lead opening, a metal plating layer on the surface of the conductive seed layer; removing the removable pattern-defining layer; and removing a part of the conductive seed layer not covered by the metal plating layer.

公开(公告)号：US20230043192A1

公开(公告)日：2023-02-09

申请号：US17789193

申请日：2021-08-16

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Liang CHEN ,  Ke WANG ,  Haoliang ZHENG ,  Minghua XUAN ,  Dongni LIU ,  Hao CHEN ,  Qi QI

IPC: H01L27/12 ,  H01L25/16 ,  H01L23/00 ,  G09G3/3233

Abstract: A display backplane is provided, including a base, wherein pixel circuits, bonding electrodes, and bonding connection wires are on the base; the bonding electrodes are coupled to the bonding connection wires in a one-to-one correspondence; the bonding electrodes and the bonding connection wires are on two opposite surfaces of the base; the pixel circuits and the bonding connection wires are on a same side of the base; one end of each bonding connection wire is coupled to the bonding electrode through the first via in the base; the other end of each of at least some bonding connection wires is coupled to the pixel circuit; and an orthographic projection of at least one of the bonding electrodes and the bonding connection wires on the base is not coincident with an orthographic projection of the pixel circuit on the base.

公开(公告)号：US20230013848A1

公开(公告)日：2023-01-19

申请号：US17783207

申请日：2021-05-20

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Lubin SHI ,  Wanpeng TENG ,  Liang CHEN ,  Bin QIN ,  Ke WANG ,  Jintao PENG ,  Fangzhen ZHANG ,  Kuanjun PENG

IPC: H01L27/32

Abstract: A display panel has a display region and a fan-out lead region, the fan-out lead region is located within the display region. The display panel comprises a base, a pixel circuit layer, a plurality of fan-out leads disposed between the base and the pixel circuit layer and located in the fan-out lead region, and an electrical field shielding pattern disposed between the pixel circuit layer and a film layer in which the plurality of fan-out leads are located. The pixel circuit layer includes a plurality of pixel circuits, at least one pixel circuit is located in the fan-out lead region. At least one fan-out lead is electrically connected to the pixel circuits. Orthographic projection of active layer patterns of transistors of the pixel circuit located in the fan-out lead region on the base are located within an orthographic projection of the electric field shielding pattern on the base.

公开(公告)号：US20220302234A1

公开(公告)日：2022-09-22

申请号：US17502052

申请日：2021-10-15

Applicant: BOE Technology Group Co., Ltd.

Inventor： Dapeng XUE ,  Shuilang DONG ,  Ke WANG ,  Zhanfeng CAO

IPC: H01L27/32 ,  H01L51/52 ,  H01L51/56 ,  H01L25/075

Abstract: A display substrate is provided, which includes a base substrate and a plurality of sub-pixels disposed on the base substrate. At least one sub-pixel includes a light transmittance region and a display region. The display region includes a circuit structure layer and a light-emitting element which are disposed on a base substrate, and the light-emitting element is connected with the circuit structure layer. The display substrate further includes a plurality of insulating layers disposed on the base substrate, and at least one insulating layer is hollowed out in the light transmittance region.

公开(公告)号：US20220302177A1

公开(公告)日：2022-09-22

申请号：US17550244

申请日：2021-12-14

Applicant: BOE Technology Group Co., Ltd.

Inventor： Yingwei LIU ,  Zhanfeng CAO ,  Ke WANG ,  Guocai ZHANG ,  Junwei YAN

IPC: H01L27/12 ,  H01L25/075 ,  H01L33/62

Abstract: A substrate includes: a base substrate; an organic layer on the base substrate with openings defined through the organic layer; a first metal layer including first metal patterns, where the first metal pattern is in the opening, and includes a first portion parallel to a bottom of the opening and a second portion parallel to a lateral wall of the opening; a second metal layer having a thickness greater than a thickness of the first metal layer; where the second metal layer includes second metal patterns, the second metal pattern is located in the opening and is in contact with the first metal layer; and, a distance from a surface of the first metal layer away from the base substrate to a plane where the base substrate is located is smaller than a distance from a surface of the organic layer away from the base substrate to the plane.

公开(公告)号：US20220123024A1

公开(公告)日：2022-04-21

申请号：US17281015

申请日：2020-01-03

Applicant: BOE Technology Group Co., Ltd.

Inventor： Zhanfeng CAO ,  Yingwei LIU ,  Ke WANG ,  Guocai ZHANG ,  Jianguo WANG ,  Zhiwei LIANG ,  Haixu LI ,  Muxin DI

IPC: H01L27/12 ,  H01L27/15

Abstract: An array substrate, a method for preparing the array substrate, and a backlight module are disclosed. Before electroplating a first metal layer on a pattern of a seed layer, the method further includes: forming a pattern of a compensation electrode wire electrically connected with a lead electrode on a side, where the lead electrode is formed, of a base substrate. The compensation electrode wire is at least on a second side of a wiring region, the pattern of the lead electrode is formed at a first side of the wiring region, and the first side and the second side are different sides. In the electroplating process, the lead electrode is connected with a negative pole of a power supply, the compensation electrode wire is electrically connected with the lead electrode, thus an area of an electroplating negative pole generating electric field lines is increased by utilizing the compensation electrode wire.

公开(公告)号：US20210210522A1

公开(公告)日：2021-07-08

申请号：US16650690

申请日：2019-10-08

Applicant: BOE Technology Group Co., Ltd.

Inventor： Yingwei LIU ,  Shuang LIANG ,  Zhiwei LIANG ,  Muxin DI ,  Ke WANG ,  Zhanfeng CAO

IPC: H01L27/12 ,  H01L25/16 ,  H01L25/065

Abstract: The disclosure relates to the technical field of display devices and discloses a display substrate, a splicing screen and a manufacturing method thereof. The display substrate includes a flexible substrate; a plurality of signal lines located at one side of the flexible substrate; a plurality of plating electrodes located at one side of the signal lines toward the flexible substrate and electrically connected to the signal lines in one-to-one correspondence; a plurality of first through holes in one-to-one correspondence to the plating electrodes and penetrating the flexible substrate and exposing the plating electrodes, the first through roles being filled with a conductive material inside; and a plurality of binding electrodes located at one side of the flexible substrate away from the signal lines and in one-to-one correspondence to the first through holes, the binding electrodes being electrically connected to corresponding plating electrode through conductive material in corresponding first through hole.