公开(公告)号：US20050102167A1

公开(公告)日：2005-05-12

申请号：US10957169

申请日：2004-09-30

Applicant: Ashok Kapoor

Inventor： Ashok Kapoor

IPC: A61B5/00 ,  G06F19/00 ,  G06Q10/00 ,  A61B5/02 ,  G06F17/60

CPC classification number: A61B5/0006 ,  A61B2560/0271 ,  G06F19/3418 ,  G06Q10/10 ,  G06Q50/24 ,  G16H40/20

Abstract: This invention teaches a method of automating some of the tasks requiring continuous data collection at the patient bedside in a hospital in a manner which significantly reduces the chances of error in providing treatment. These tasks include provisioning of the IV pumps or other fluid infusion pumps, feed pumps, oxygen delivery systems, gathering, recording, storing, and analyzing signals from ECG machine or pulse oxymeter or any other medical device. This invention teaches the use of wireless transceiver modules which are connected to the data ports on the medical instrument to gather the data and transmit the data to a wireless access point. Protocols to identify the patient, care provider, medicine, equipment, and treatment are described. Use of an external means for verifying the identity of the medical device and the medicine is also described.

Abstract translation: 本发明教导了一种方法，其以在显着降低提供治疗的错误机会的方式自动化需要在医院的患者床边连续数据收集的一些任务。 这些任务包括提供IV泵或其他液体输注泵，给水泵，氧气输送系统，收集，记录，存储和分析来自ECG机器或脉搏氧气计或任何其他医疗设备的信号。 本发明教导了使用连接到医疗仪器上的数据端口的无线收发器模块来收集数据并将数据发送到无线接入点。 描述了确定患者，护理提供者，药物，设备和治疗的方案。 还描述了使用用于验证医疗装置和药物的身份的外部装置。

公开(公告)号：US5719733A

公开(公告)日：1998-02-17

申请号：US556599

申请日：1995-11-13

Applicant: Hua-Fang Wei ,  Ashok Kapoor

Inventor： Hua-Fang Wei ,  Ashok Kapoor

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H02H3/22 ,  H01L23/62

CPC classification number: H01L27/0259 ,  H01L2924/0002

Abstract: Apparatus and process for making the apparatus for electrostatic discharge (ESD) protection of an electronic device, using a silicon controlled rectifier (SCR) configuration. A spaced apart p-well and n-well are formed in a substrate, and spaced apart p+ and n+ contact regions are formed in each well, with an additional n+ or p+ drain tap contiguous to and lying between the two wells. The wells may be formed by a retrograde process or by a conventional process, with or without an epitaxial layer. A first electrode (ground) is connected to the p+ and n+ contact regions and through a polysilicon region to a gate oxide region in the first well. The polysilicon region has a small, controlled poly length. A second electrode is connected to the p+ and n+ contact regions in the second well and to an electrical circuit to be protected against ESD. The second well may be replaced by a portion of the substrate, of opposite electrical polarity to the first well. The triggering voltage for snapback of the SCR device is tunable over a voltage range as low as 5-11 Volts, and the device dynamical resistance in the on-state is about 8-9 Ohms. The SCR device has reduced tradeoff with latchup behavior of the electronic device to be protected.

Abstract translation: 使用可控硅整流（SCR）配置制造电子设备的静电放电（ESD）保护装置的设备和方法。 在衬底中形成间隔开的p阱和n阱，并且在每个阱中形成间隔开的p +和n +接触区，其中附加的n +或p +漏极抽头邻接并位于两个阱之间。 孔可以通过逆向工艺或通过常规工艺形成，具有或不具有外延层。 第一电极（接地）连接到p +和n +接触区域并且通过多晶硅区域连接到第一阱中的栅极氧化物区域。 多晶硅区域具有小的可控聚长度。 第二电极连接到第二阱中的p +和n +接触区域以及被保护以防止ESD的电路。 第二个井可以被与第一井相反的电极性的一部分基板所取代。 SCR器件的快速恢复触发电压在低至5-11伏特的电压范围内是可调谐的，并且导通状态下的器件动态电阻约为8-9欧姆。 SCR装置已经减少了要保护的电子装置的闩锁行为的折衷。

公开(公告)号：US5656850A

公开(公告)日：1997-08-12

申请号：US396542

申请日：1995-03-01

Applicant: Ashok Kapoor

Inventor： Ashok Kapoor

IPC: H01L27/118

CPC classification number: H01L27/11803 ,  Y10S257/909

Abstract: A microelectronic integrated circuit includes a semiconductor substrate, and a plurality of microelectronic devices formed on the substrate. Each device has a periphery defined by a hexagon, and includes an active area formed within the periphery. A first terminal and a second terminal are formed in the active area adjacent to edges of the hexagon that are separated by another edge. First to third gates are formed between the first and second terminals, and have gate terminals formed outside the active area adjacent to other edges of the hexagon. The power supply connections to the first and second terminals, the conductivity type (NMOS or PMOS), and the addition of a pull-up or a pull-down resistor is selected for each device to provide a desired AND, NAND, OR or NOR function. The devices are interconnected using three direction routing based on hexagonal geometry.

Abstract translation: 微电子集成电路包括半导体衬底和形成在衬底上的多个微电子器件。 每个装置具有由六边形限定的周边，并且包括在周边内形成的有效区域。 第一端子和第二端子形成在与另一边缘分离的六边形边缘相邻的有源区域中。 第一至第三栅极形成在第一和第二端子之间，并且具有形成在与六边形的其它边缘相邻的有源区域外部的栅极端子。 为每个器件选择与第一和第二端子的电源连接，导电类型（NMOS或PMOS）以及上拉或下拉电阻的添加，以提供所需的AND，NAND，或或NOR 功能。 这些设备使用基于六边形几何的三向路由进行互连。

公开(公告)号：US5539246A

公开(公告)日：1996-07-23

申请号：US396560

申请日：1995-03-01

Applicant: Ashok Kapoor

Inventor： Ashok Kapoor

IPC: H01L27/118

CPC classification number: H01L27/11803 ,  Y10S257/909

Abstract: A microelectronic integrated circuit includes a semiconductor substrate, and a plurality of microelectronic devices formed on the substrate. Each device has a periphery defined by a hexagon, and includes an active area formed within the periphery, a central terminal formed in a central portion of the active area, and interconnected first to third terminals formed in the active area adjacent to edges of the hexagon that are separated by other edges. First to third gates are formed between the first to third terminals respectively and the central terminal, and have contacts formed outside the active area adjacent to the other edges of the hexagon. The power supply connections to the central terminal and the first to third terminals, the conductivity type (NMOS or PMOS), and the addition of a pull-up or a pull-down resistor is selected for each device to provide a desired OR, NOR, AND or NAND function. The devices are interconnected using three direction routing based on hexagonal geometry.

Abstract translation: 微电子集成电路包括半导体衬底和形成在衬底上的多个微电子器件。 每个装置具有由六边形限定的周边，并且包括形成在周边内的有源区域，形成在有源区域的中心部分中的中心端子，以及形成在与六边形边缘相邻的有源区域中的互连的第一至第三端子 被其他边缘分隔开。 第一至第三栅极分别形成在第一至第三端子和中心端子之间，并且具有形成在与六边形的其他边缘相邻的有源区域外部的触点。 为每个器件选择与中心端子和第一至第三端子的电源连接，导电类型（NMOS或PMOS）以及上拉或下拉电阻的添加，以提供所需的OR，NOR ，AND或NAND功能。 这些设备使用基于六边形几何的三向路由进行互连。

公开(公告)号：US20070096144A1

公开(公告)日：2007-05-03

申请号：US11261873

申请日：2005-10-28

Applicant: Ashok Kapoor

Inventor： Ashok Kapoor

IPC: H01L31/111 ,  H01L21/337

CPC classification number: H01L29/808 ,  H01L21/2257 ,  H01L27/0611 ,  H01L27/098 ,  H01L29/41783 ,  H01L29/456 ,  H01L29/66492 ,  H01L29/66901 ,  H01L29/7833

Abstract: This invention describes a method of building complementary logic circuits using junction field effect transistors in silicon. This invention is ideally suited for deep submicron dimensions, preferably below 65 nm. The basis of this invention is a complementary Junction Field Effect Transistor which is operated in the enhancement mode. The speed-power performance of the JFETs becomes comparable with the CMOS devices at sub-70 nanometer dimensions. However, the maximum power supply voltage for the JFETs is still limited to below the built-in potential (a diode drop). To satisfy certain applications which require interface to an external circuit driven to higher voltage levels, this invention includes the structures and methods to build CMOS devices on the same substrate as the JFET devices.

Abstract translation: 本发明描述了使用硅中的结型场效应晶体管构建互补逻辑电路的方法。 本发明理想地适用于深亚微米尺寸，优选低于65nm。 本发明的基础是在增强模式下操作的互补结型场效应晶体管。 JFET的速度功率性能可以与次级70纳米尺寸的CMOS器件相媲美。 然而，JFET的最大电源电压仍然限制在低于内置电位（二极管压降）。 为了满足需要与驱动到更高电压电平的外部电路接口的某些应用，本发明包括在与JFET器件相同的衬底上构建CMOS器件的结构和方法。

公开(公告)号：US20060006479A1

公开(公告)日：2006-01-12

申请号：US11027181

申请日：2004-12-29

Applicant: Ashok Kapoor

Inventor： Ashok Kapoor

IPC: H01L29/76

CPC classification number: G11C11/4023 ,  G11C11/404 ,  G11C11/412 ,  G11C16/0416 ,  H01L27/1104

Abstract: In deep submicron memory arrays there is noted a relatively steady on current value and, therefore, threshold values of the transistors comprising the memory cell are reduced. This, in turn, results in an increase in the leakage current of the memory cell. With the use of an ever increasing number of memory cells leakage current must be controlled. A method and apparatus using a dynamic threshold voltage control scheme implemented with no more than minor changes to the existing MOS process technology is disclosed. The disclosed invention controls the threshold voltage of MOS transistors. Methods for enhancing the impact of the dynamic threshold control technology using this apparatus are also included. The invention is particularly useful for SRAM, DRAM, and NVM devices.

Abstract translation: 在深亚微米存储器阵列中，注意到电流值相对稳定，因此减小了包括存储器单元的晶体管的阈值。 这又导致存储单元的漏电流的增加。 随着使用越来越多的存储单元，必须控制漏电流。 公开了一种利用动态阈值电压控制方案实现的方法和装置，其中仅对现有的MOS处理技术进行了微小的改变。 所公开的发明控制MOS晶体管的阈值电压。 还包括用于增强使用该装置的动态阈值控制技术的影响的方法。 本发明对SRAM，DRAM和NVM器件特别有用。

公开(公告)号：US5867423A

公开(公告)日：1999-02-02

申请号：US838799

申请日：1997-04-10

Applicant: Ashok Kapoor ,  Alex Owens ,  Thomas R. Wik ,  Raymond T. Leung ,  V. Swamy Irrinki

Inventor： Ashok Kapoor ,  Alex Owens ,  Thomas R. Wik ,  Raymond T. Leung ,  V. Swamy Irrinki

IPC: G11C16/04 ,  G11C11/56 ,  G11C16/02 ,  H01L21/8246 ,  H01L27/112

CPC classification number: G11C11/5692 ,  G11C7/16

Abstract: A circuit and method which enables storage of more than two logic states in a memory cell by selectively setting threshold voltages of transistors in a memory array according to the present invention. In one embodiment, a memory circuit includes an array of storage transistors. Each storage transistor has a gate connected to an associated read line. When a read line is asserted, the current which flows through a selected storage transistor is indicative of the stored logic state. The current through each transistor is individually selected by setting the threshold voltage of each storage transistor during manufacture. Different transistors in the array are configured with differing threshold voltages to thereby represent different storage states. An analog-to-digital (A/D) converter is coupled to the selected storage transistor so as to sense the current and determine the state represented. Since each cell may represent one of more than two storage states, the memory circuit may advantageously allow an increased number of bits to be stored in each memory cell, thereby increasing the storage density and reducing the cost per bit.

Abstract translation: 根据本发明，通过选择性地设置存储器阵列中的晶体管的阈值电压，能够在存储器单元中存储多于两个逻辑状态的电路和方法。 在一个实施例中，存储电路包括存储晶体管阵列。 每个存储晶体管具有连接到相关读取线的栅极。 当读线被确认时，流经所选择的存储晶体管的电流指示存储的逻辑状态。 通过在制造期间设置每个存储晶体管的阈值电压来分别选择通过每个晶体管的电流。 阵列中的不同晶体管配置有不同的阈值电压，从而表示不同的存储状态。 模数（A / D）转换器耦合到选定的存储晶体管，以便感测电流并确定所表示的状态。 由于每个单元可以表示多于两个存储状态之一，所以存储器电路可以有利地允许将更多数量的位存储在每个存储单元中，从而增加存储密度并降低每位的成本。

公开(公告)号：US5808932A

公开(公告)日：1998-09-15

申请号：US779991

申请日：1996-12-23

Applicant: V. Swamy Irrinki ,  Ashok Kapoor ,  Raymond T. Leung ,  Alex Owens ,  Thomas R. Wik

Inventor： V. Swamy Irrinki ,  Ashok Kapoor ,  Raymond T. Leung ,  Alex Owens ,  Thomas R. Wik

IPC: G11C11/41 ,  G11C11/56 ,  G11C11/24

CPC classification number: G11C11/565 ,  G11C7/16

Abstract: A memory circuit which enables storage of more than two logic states in a memory cell. Since the additional logic states may be used to represent additional information bits, this memory circuit increases the number of bits that may be stored per memory cell, thereby increasing the storage density and reducing the cost per bit. The disclosed memory circuit comprises an analog-to-digital converter coupled to detect a current through a transistor in a memory cell. The current is determined by a charge stored on the transistor's gate. By enabling the current to be detected in discrete increments, it becomes possible to represent more than one bit of information with the charge stored in the memory cell. Usage of additional increments necessitates more precise storage and detection circuitry. In one embodiment, the storage circuitry uses feedback to obtain a greater logic state retrieval accuracy.

Abstract translation: 一种能够在存储器单元中存储多于两个逻辑状态的存储器电路。 由于附加逻辑状态可用于表示附加信息位，所以该存储器电路增加了每个存储单元可以存储的位数，由此增加了存储密度并降低了每位的成本。 所公开的存储器电路包括耦合以检测通过存储器单元中的晶体管的电流的模拟 - 数字转换器。 电流由存储在晶体管门上的电荷决定。 通过使能够以离散增量检测电流，可以用存储在存储单元中的电荷来表示多于一位的信息。 额外增量的使用需要更精确的存储和检测电路。 在一个实施例中，存储电路使用反馈来获得更大的逻辑状态检索精度。

公开(公告)号：US5674774A

公开(公告)日：1997-10-07

申请号：US474794

申请日：1995-06-07

Applicant: Nicholas F. Pasch ,  Ashok Kapoor ,  Richard D. Schinella

Inventor： Nicholas F. Pasch ,  Ashok Kapoor ,  Richard D. Schinella

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/335

CPC classification number: H01L29/66575 ,  H01L21/2652 ,  H01L29/41783 ,  H01L29/6659 ,  H01L29/665 ,  H01L29/66545

Abstract: Remote electrical contacts for a semiconductor are produced by depositing a polysilicon layer over the entire surface of a semiconductor device and removing a portion of the polysilicon layer by chemi-mechanical polishing. The resulting structure is thereby provided with electrically isolated areas of polysilicon which constitute remote electrical contacts for the semiconductor device. The polysilicon layer or the isolated areas of polysilicon can be salicided to provide very low resistivity. Either the polysilicon layer or the salicide layer can be subjected to ion implantation to provide LDD regions.

Abstract translation: 通过在半导体器件的整个表面上沉积多晶硅层并通过化学机械抛光去除多晶硅层的一部分来制造用于半导体的远程电触点。 所得到的结构由此提供构成用于半导体器件的远程电触点的电绝缘的多晶硅区域。 多晶硅层或多晶硅的隔离区域可以被水化以提供非常低的电阻率。 可以对多晶硅层或自对接硅化物层进行离子注入以提供LDD区域。

公开(公告)号：US5521108A

公开(公告)日：1996-05-28

申请号：US121679

申请日：1993-09-15

Applicant: Michael D. Rostoker ,  Ashok Kapoor

Inventor： Michael D. Rostoker ,  Ashok Kapoor

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L29/423

CPC classification number: H01L29/66825 ,  H01L21/2807 ,  H01L27/11517 ,  H01L29/42324 ,  Y10S148/059

Abstract: A conductive member is described with a surface of controlled roughness thereon which is useful in the construction of an integrated circuit structure. In a preferred embodiment, the conductive member is formed using a mixture of germanium and silicon which is then oxidized, resulting in the formation of a roughened surface on the germanium/silicon conductive member due to the difference in the respective rates of oxidation of the germanium and silicon. After oxidation of the conductive member, the oxide layer may be removed, leaving the roughened surface on the germanium/silicon conductive member. When an integrated circuit structure such as an EPROM is to be formed using this conductive member with a roughened surface, a further layer of oxide is then deposited over the roughened surface followed by deposition of a second layer of conductive material such as polysilicon or a germanium/silicon mixture, from which the control gate will be formed. A further oxide layer may then be formed over the second conductive layer followed by a patterning step to respectively form the floating gate (from the germanium/silicon layer) and the control gate from the second conductive layer.

Abstract translation: 描述了导电构件，其上具有受控粗糙度的表面，其可用于集成电路结构的构造。 在优选实施例中，使用锗和硅的混合物形成导电构件，然后将其氧化，导致在锗/硅导电构件上形成粗糙表面，这是由于锗的氧化速率的差异 和硅。 在氧化导电部件之后，可以去除氧化物层，使锗/硅导电部件上的粗糙表面残留。 当使用具有粗糙表面的导电部件形成诸如EPROM的集成电路结构时，然后在粗糙表面上沉积另外的氧化物层，随后沉积第二层导电材料，例如多晶硅或锗 /硅混合物，从其形成控制栅极。 然后可以在第二导电层上形成另外的氧化物层，接着形成图案化步骤以分别从第二导电层形成浮栅（来自锗/硅层）和控制栅极。