公开(公告)号：US11251364B2

公开(公告)日：2022-02-15

申请号：US16773232

申请日：2020-01-27

Applicant: Applied Materials, Inc.

Inventor： Lin Xue ,  Chi Hong Ching ,  Jaesoo Ahn ,  Mahendra Pakala ,  Rongjun Wang

IPC: H01L27/22 ,  H01L43/08 ,  G11C11/16 ,  G11C11/15 ,  H01L21/768 ,  H01L45/00 ,  H01L27/24 ,  G11B5/31 ,  G11B5/39

Abstract: Embodiments herein provide film stacks that include a buffer layer; a synthetic ferrimagnet (SyF) coupling layer; and a capping layer, wherein the capping layer comprises one or more layers, and wherein the capping layer, the buffer layer, the SyF coupling layer, or a combination thereof, is not fabricated from Ru.

公开(公告)号：US20210234091A1

公开(公告)日：2021-07-29

申请号：US16752013

申请日：2020-01-24

Applicant: APPLIED Materials, Inc.

Inventor： Jong Mun Kim ,  Mang-Mang Ling ,  Soham Asrani ,  Lin Xue ,  Chentsau Chris Ying ,  Srinivas D. Nemani ,  Ellie Y. Yieh

IPC: H01L43/12 ,  H01L43/10

Abstract: A method of etching a layer stack. The method may include providing a substrate in a process chamber, the substrate comprising an array of patterned features, arranged within a layer stack, the layer stack including at least one metal layer, and directing an ion beam to the substrate from an ion source, wherein the ion beam causes a physical sputtering of the at least one metal layer. The method may include directing a neutral reactive gas directly to the substrate, separately from the ion source, wherein the neutral reactive gas reacts with metallic species generated by the physical sputtering of the at least one metal layer.

公开(公告)号：US10944050B2

公开(公告)日：2021-03-09

申请号：US16351850

申请日：2019-03-13

Applicant: Applied Materials, Inc.

Inventor： Lin Xue ,  Chi Hong Ching ,  Rongjun Wang ,  Mahendra Pakala

IPC: H01L29/82 ,  H01L43/12 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: Embodiments of magnetic tunnel junction (MTJ) structures discussed herein employ seed layers of one or more layer of chromium (Cr), NiCr, NiFeCr, RuCr, IrCr, or CoCr, or combinations thereof. These seed layers are used in combination with one or more pinning layers, a first pinning layer in contact with the seed layer can contain a single layer of cobalt, or can contain cobalt in combination with bilayers of cobalt and platinum (Pt), iridium (Ir), nickel (Ni), or palladium (Pd), The second pinning layer can be the same composition and configuration as the first, or can be of a different composition or configuration. The MTJ stacks discussed herein maintain desirable magnetic properties subsequent to high temperature annealing.

公开(公告)号：US11374170B2

公开(公告)日：2022-06-28

申请号：US16141470

申请日：2018-09-25

Applicant: Applied Materials, Inc.

Inventor： Lin Xue ,  Jaesoo Ahn ,  Hsin-wei Tseng ,  Mahendra Pakala

IPC: H01L43/12 ,  H01L43/10

Abstract: Embodiments of the disclosure relate to methods for fabricating structures used in memory devices. More specifically, embodiments of the disclosure relate to methods for fabricating MTJ structures in memory devices. In one embodiment, the method includes forming a MTJ structure, depositing a encapsulating layer on a top and sides of the MTJ structure, depositing a dielectric material on the encapsulating layer, removing the dielectric material and the encapsulating layer disposed on the top of the MTJ structure by a chemical mechanical planarization (CMP) process to expose the top of the MTJ structure, and depositing a contact layer on the MTJ structure. The method utilizes a CMP process to expose the top of the MTJ structure instead of an etching process, which avoids damaging the MTJ structure and leads to improved electrical contact between the MTJ structure and the contact layer.

公开(公告)号：US11245069B2

公开(公告)日：2022-02-08

申请号：US15199006

申请日：2016-06-30

Applicant: Applied Materials, Inc.

Inventor： Lin Xue ,  Jaesoo Ahn ,  Mahendra Pakala ,  Chi Hong Ching ,  Rongjun Wang

IPC: H01L43/12 ,  H01L43/08 ,  H01L43/10 ,  H01F10/14 ,  H01F10/32

Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate in for spin-transfer-torque magnetoresistive random access memory (STT-MRAM) applications. In one embodiment, the method includes patterning a film stack having a tunneling barrier layer disposed between a magnetic reference layer and a magnetic storage layer disposed on a substrate to remove a portion of the film stack from the substrate until an upper surface of the substrate is exposed, forming a sidewall passivation layer on sidewalls of the patterned film stack and subsequently performing a thermal annealing process to the film stack.

公开(公告)号：US11239086B2

公开(公告)日：2022-02-01

申请号：US16396226

申请日：2019-04-26

Applicant: Applied Materials, Inc.

Inventor： Hsin-wei Tseng ,  Mahendra Pakala ,  Lin Xue ,  Jaesoo Ahn ,  Sajjad Amin Hassan

IPC: H01L21/306 ,  H01L23/544 ,  H01L21/822 ,  G03F9/00

Abstract: Embodiments described herein relate to substrate processing methods. More specifically, embodiments of the disclosure provide for an MRAM back end of the line integration process which utilizes a zero mark for improved patterning alignment. In one embodiment, the method includes fabricating a substrate having at least a bottom contact and a via extending from the bottom contact in a first region and etching a zero mark in the substrate in a second region apart from the first region. The method also includes depositing a touch layer over the substrate in the first region and the second region, depositing a memory stack over the touch layer in the first region and the second region, and depositing a hardmask over the memory stack layer in the first region and the second region.

公开(公告)号：US10957849B2

公开(公告)日：2021-03-23

申请号：US16358475

申请日：2019-03-19

Applicant: Applied Materials, Inc.

Inventor： Lin Xue ,  Chi Hong Ching ,  Rongjun Wang ,  Mahendra Pakala

IPC: H01L43/10 ,  H01L27/22 ,  H01L43/08

Abstract: Embodiments of magnetic tunnel junction (MTJ) structures discussed herein employ a first pinning layer and a second pinning layer with a synthetic anti-ferrimagnetic layer disposed therebetween. The first pinning layer in contact with the seed layer can contain a single layer of platinum or palladium, alone or in combination with one or more bilayers of cobalt and platinum (Pt), nickel (Ni), or palladium (Pd), or combinations or alloys thereof, The first pinning layer and the second pinning layer can have a different composition or configuration such that the first pinning layer has a higher magnetic material content than the second pinning layer and/or is thicker than the second pinning layer. The MTJ stacks discussed herein maintain desirable magnetic properties subsequent to high temperature annealing.

公开(公告)号：US09564582B2

公开(公告)日：2017-02-07

申请号：US14201439

申请日：2014-03-07

Applicant: Applied Materials, Inc.

Inventor： Mahendra Pakala ,  Mihaela Balseanu ,  Jonathan Germain ,  Jaesoo Ahn ,  Lin Xue

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/08

CPC classification number: H01L43/12 ,  H01L27/222 ,  H01L43/08

Abstract: A method for fabricating an MRAM bit that includes depositing a spacer layer that protects the tunneling barrier layer during processing is disclosed. The deposited spacer layer prevents byproducts formed in later processing from redepositing on the tunneling barrier layer. Such redeposition may lead to product failure and decreased manufacturing yield. The method further includes non-corrosive processing conditions that prevent damage to the layers of MRAM bits. The non-corrosive processing conditions may include etching without using a halogen-based plasma. Embodiments disclosed herein use an etch-deposition-etch sequence that simplifies processing.

Abstract translation: 公开了一种用于制造MRAM位的方法，其包括在处理期间沉积保护隧道势垒层的间隔层。 沉积的间隔层防止在后续处理中形成的副产物再沉积在隧道势垒层上。 这种再沉积可能导致产品失效并降低了制造成品率。 该方法还包括防腐损坏处理条件，以防损坏MRAM位的层。 非腐蚀性处理条件可以包括不使用卤素等离子体的蚀刻。 本文公开的实施例使用简化处理的蚀刻 - 沉积蚀刻序列。

公开(公告)号：US12201030B2

公开(公告)日：2025-01-14

申请号：US18231414

申请日：2023-08-08

Applicant: Applied Materials, Inc.

Inventor： Minrui Yu ,  Wenhui Wang ,  Jaesoo Ahn ,  Jong Mun Kim ,  Sahil Patel ,  Lin Xue ,  Chando Park ,  Mahendra Pakala ,  Chentsau Chris Ying ,  Huixiong Dai ,  Christopher S. Ngai

IPC: H10N50/10 ,  G01R33/09 ,  G11C11/16 ,  H10B61/00 ,  H10N50/85 ,  H10N52/01 ,  H10N52/80

Abstract: Embodiments of the present disclosure generally include spin-orbit torque magnetoresistive random-access memory (SOT-MRAM) devices and methods of manufacture thereof. The SOT-MRAM devices described herein include an SOT layer laterally aligned with a magnetic tunnel junction (MTJ) stack and formed over a trench in an interconnect. Thus, the presence of the SOT layer outside the area of the MTJ stack is eliminated, and electric current passes from the interconnect to the SOT layer by SOT-interconnect overlap. The devices and methods described herein reduce the formation of shunting current and enable the MTJ to self-align with the SOT layer in a single etching process.

公开(公告)号：US11621393B2

公开(公告)日：2023-04-04

申请号：US17112484

申请日：2020-12-04

Applicant: Applied Materials, Inc.

Inventor： Lin Xue ,  Chando Park ,  Chi Hong Ching ,  Jaesoo Ahn ,  Mahendra Pakala

IPC: H01L43/12 ,  C23C14/06 ,  C23C14/54 ,  H01F10/32 ,  H01F41/32 ,  H01L43/10 ,  H01L43/02 ,  H01F10/13 ,  H01L21/67 ,  C23C14/00 ,  H01F41/30 ,  H01F10/30 ,  G11C11/16

Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate for MRAM applications. In one embodiment, a magnetic tunnel junction (MTJ) device structure includes a junction structure disposed on a substrate, the junction structure comprising a first ferromagnetic layer and a second ferromagnetic layer sandwiching a tunneling barrier layer, a dielectric capping layer disposed on the junction structure, a metal capping layer disposed on the junction structure, and a top buffer layer disposed on the metal capping layer.