公开(公告)号：US11908678B2

公开(公告)日：2024-02-20

申请号：US17149399

申请日：2021-01-14

Applicant: Applied Materials, Inc.

Inventor： Lan Yu ,  Benjamin D. Briggs ,  Tyler Sherwood ,  Raghav Sreenivasan ,  Joseph Salfelder

IPC: H01L21/02 ,  H01L21/4757

CPC classification number: H01L21/02024 ,  H01L21/02019 ,  H01L21/47573

Abstract: Processing methods may be performed to form a filled contact hole in a mirror layer of a semiconductor substrate. The method may include forming a contact hole through a mirror layer of the semiconductor substrate by an etch process. The method may include filling the contact hole with a fill material. A portion of the fill material may overlie the mirror layer. The method may also include removing a portion of the fill material external to the contact hole by chemical mechanical polishing landing on the mirror layer.

公开(公告)号：US11605741B2

公开(公告)日：2023-03-14

申请号：US17102148

申请日：2020-11-23

Applicant: Applied Materials, Inc.

Inventor： Joshua S. Holt ,  Lan Yu ,  Tyler Sherwood ,  Archana Kumar ,  Nicolas Louis Gabriel Breil ,  Siddarth Krishnan

IPC: H01L29/872 ,  H01L21/28 ,  H01L29/45 ,  H01L29/861 ,  H01L29/66 ,  H01L29/47

Abstract: Exemplary methods of forming a semiconductor structure may include forming a layer of metal on a semiconductor substrate. The layer of metal may extend along a first surface of the semiconductor substrate. The semiconductor substrate may be or include silicon. The methods may include performing an anneal to produce a metal silicide. The methods may include implanting ions in the metal silicide to increase a barrier height over 0.65 V.

公开(公告)号：US11586067B2

公开(公告)日：2023-02-21

申请号：US17100407

申请日：2020-11-20

Applicant: Applied Materials, Inc.

Inventor： Lan Yu ,  Benjamin D. Briggs ,  Tyler Sherwood ,  Raghav Sreenivasan

IPC: G02F1/1335 ,  G02F1/1362

Abstract: Processing methods may be performed to form a pixel material in a semiconductor substrate. The methods may include forming a lithographic mask overlying the semiconductor substrate. The lithographic mask may include a window. The method may include forming a via in the semiconductor substrate by a dry etch process through the window. The method may also include forming the pixel material by depositing a fill material in the via.

公开(公告)号：US20220310531A1

公开(公告)日：2022-09-29

申请号：US17214411

申请日：2021-03-26

Applicant: Applied Materials, Inc.

Inventor： Amirhasan Nourbakhsh ,  Lan Yu ,  Joseph F. Salfelder ,  Ki Cheol Ahn ,  Tyler Sherwood ,  Siddarth Krishnan ,  Michael Jason Fronckowiak ,  Xing Chen

IPC: H01L23/00 ,  H01L21/311 ,  H01L21/308 ,  H01L21/304

Abstract: Exemplary methods of processing a semiconductor substrate may include forming a layer of dielectric material on the semiconductor substrate. The methods may include performing an edge exclusion removal of the layer of dielectric material. The methods may include forming a mask material on the semiconductor substrate. The mask material may contact the dielectric material at an edge region of the semiconductor substrate. The methods may include patterning an opening in the mask material overlying a first surface of the semiconductor substrate. The methods may include etching one or more trenches through the semiconductor substrate.

公开(公告)号：US20220223402A1

公开(公告)日：2022-07-14

申请号：US17149399

申请日：2021-01-14

Applicant: Applied Materials, Inc.

Inventor： Lan Yu ,  Benjamin D. Briggs ,  Tyler Sherwood ,  Raghav Sreenivasan ,  Joseph Salfelder

IPC: H01L21/02 ,  H01L21/4757

Abstract: Processing methods may be performed to form a filled contact hole in a mirror layer of a semiconductor substrate. The method may include forming a contact hole through a mirror layer of the semiconductor substrate by an etch process. The method may include filling the contact hole with a fill material. A portion of the fill material may overlie the mirror layer. The method may also include removing a portion of the fill material external to the contact hole by chemical mechanical polishing landing on the mirror layer.

公开(公告)号：US20220165574A1

公开(公告)日：2022-05-26

申请号：US17102148

申请日：2020-11-23

Applicant: Applied Materials, Inc.

Inventor： Joshua S. Holt ,  Lan Yu ,  Tyler Sherwood ,  Archana Kumar ,  Nicolas Louis Gabriel Breil ,  Siddarth Krishnan

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/861 ,  H01L29/45

Abstract: Exemplary methods of forming a semiconductor structure may include forming a layer of metal on a semiconductor substrate. The layer of metal may extend along a first surface of the semiconductor substrate. The semiconductor substrate may be or include silicon. The methods may include performing an anneal to produce a metal silicide. The methods may include implanting ions in the metal silicide to increase a barrier height over 0.65 V.

公开(公告)号：US20220163845A1

公开(公告)日：2022-05-26

申请号：US17100407

申请日：2020-11-20

Applicant: Applied Materials, Inc.

Inventor： Lan Yu ,  Benjamin D. Briggs ,  Tyler Sherwood ,  Raghav Sreenivasan

IPC: G02F1/1335 ,  H01L21/768 ,  G02F1/1362

Abstract: Processing methods may be performed to form a pixel material in a semiconductor substrate. The methods may include forming a lithographic mask overlying the semiconductor substrate. The lithographic mask may include a window. The method may include forming a via in the semiconductor substrate by a dry etch process through the window. The method may also include forming the pixel material by depositing a fill material in the via.

公开(公告)号：US20220163834A1

公开(公告)日：2022-05-26

申请号：US17100400

申请日：2020-11-20

Applicant: Applied Materials, Inc.

Inventor： Lan Yu ,  Benjamin D. Briggs ,  Tyler Sherwood ,  Zihao Yang

IPC: G02F1/1339 ,  H01L21/66

Abstract: Processing methods may be performed to form a pixel isolation structure on a semiconductor substrate. The method may include forming a pixel isolation bilayer on the semiconductor substrate. The pixel isolation bilayer may include a high-k layer overlying a stopping layer. The method may include forming a lithographic mask on a first region of the pixel isolation bilayer. The method may also include etching the pixel isolation bilayer external to the first region. The etching may reveal the semiconductor substrate. The etching may form the pixel isolation structure.

公开(公告)号：US20220163707A1

公开(公告)日：2022-05-26

申请号：US17100416

申请日：2020-11-20

Applicant: Applied Materials, Inc.

Inventor： Lan Yu ,  Benjamin D. Briggs ,  Tyler Sherwood ,  Raghav Sreenivasan

IPC: G02B5/08

Abstract: Processing methods may be performed to form a grounded mirror structure on a semiconductor substrate. The methods may include revealing a metal layer. The metal layer may underlie a spacer layer. The metal layer may be revealed by a dry etch process. The method may include forming a mirror layer overlying the spacer layer and the metal layer. The mirror layer may contact the metal layer. The method may also include forming an oxide inclusion overlying a portion of the mirror layer. The portion of the mirror layer may be external to the spacer layer.

公开(公告)号：US11908914B2

公开(公告)日：2024-02-20

申请号：US17376504

申请日：2021-07-15

Applicant: Applied Materials, Inc.

Inventor： Ria Someshwar ,  Seshadri Ganguli ,  Lan Yu ,  Siddarth Krishnan ,  Srinivas Gandikota ,  Jacqueline S. Wrench ,  Yixiong Yang

IPC: H01L29/45 ,  H01L21/324 ,  H01L21/285 ,  H01L29/40 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L29/456 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/823814 ,  H01L29/401 ,  H01L29/45 ,  H01L29/665

Abstract: Methods for forming a semiconductor structure and semiconductor structures are described. The method comprises patterning a substrate to form a first opening and a second opening, the substrate comprising an n transistor and a p transistor, the first opening over the n transistor and the second opening over the p transistor; pre-cleaning the substrate; depositing a titanium silicide (TiSi) layer on the n transistor and on the p transistor by plasma-enhanced chemical vapor deposition (PECVD); optionally depositing a first barrier layer on the titanium silicide (TiSi) layer and selectively removing the first barrier layer from the p transistor; selectively forming a molybdenum silicide (MoSi) layer on the titanium silicide (TiSi) layer on the n transistor and the p transistor; forming a second barrier layer on the molybdenum silicide (MoSi) layer; and annealing the semiconductor structure. The method may be performed in a processing chamber without breaking vacuum.