公开(公告)号：US10818510B2

公开(公告)日：2020-10-27

申请号：US16260041

申请日：2019-01-28

Applicant: Applied Materials, Inc.

Inventor： Tobin Kaufman-Osborn ,  Keith Tatseun Wong

IPC: H01L21/32 ,  H01L21/3105 ,  H01L21/768

Abstract: Implementations described herein generally relate to processes for the fabrication of semiconductor devices in which a self-assembled monolayer (SAM) is used to achieve selective area deposition. Methods described herein relate to alternating SAM molecule and hydroxyl moiety exposure operations which may be utilized to form SAM layers suitable for blocking deposition of subsequently deposited materials.

公开(公告)号：US10192752B2

公开(公告)日：2019-01-29

申请号：US15446816

申请日：2017-03-01

Applicant: Applied Materials, Inc.

Inventor： Tobin Kaufman-Osborn ,  Keith Tatseun Wong

IPC: H01L21/32 ,  H01L21/3105

Abstract: Implementations described herein generally relate to processes for the fabrication of semiconductor devices in which a self-assembled monolayer (SAM) is used to achieve selective area deposition. Methods described herein relate to alternating SAM molecule and hydroxyl moiety exposure operations which may be utilized to form SAM layers suitable for blocking deposition of subsequently deposited materials.

公开(公告)号：US10062561B2

公开(公告)日：2018-08-28

申请号：US15360016

申请日：2016-11-23

Applicant: Applied Materials, Inc.

Inventor： Kurtis S Leschkies ,  Keith Tatseun Wong ,  Steven Verhaverbeke

IPC: H01L21/31 ,  H01L21/02

CPC classification number: H01L21/02203 ,  H01L21/02337 ,  H01L21/02348 ,  H01L21/31111 ,  H01L21/67109 ,  H01L21/67126 ,  H01L21/6719 ,  H01L21/67303

Abstract: Methods are described for reducing the wet etch rate of dielectric films formed on a patterned substrate by flowing the material into gaps during deposition. Films deposited in this manner may initially exhibit elevated wet etch rates. The dielectric films are treated by exposing the patterned substrate to a high pressure of water vapor in the gas phase. The treatment may reduce the wet etch rate of the dielectric films, especially the gapfill portion of the dielectric film. Scanning electron microscopy has confirmed that the quantity and/or size of pores is reduced or eliminated by the procedures described herein. The treatment has also been found to reduce the etch rate, e.g., at the bottom of gaps filled with the dielectric film.

公开(公告)号：US12198951B2

公开(公告)日：2025-01-14

申请号：US15917365

申请日：2018-03-09

Applicant: Applied Materials, Inc.

Inventor： Qiwei Liang ,  Srinivas D. Nemani ,  Adib Khan ,  Venkata Ravishankar Kasibhotla ,  Sultan Malik ,  Sean S. Kang ,  Keith Tatseun Wong

IPC: H01L21/67 ,  C23C16/52 ,  H01L21/324 ,  H01L21/687 ,  H01L21/768

Abstract: A high-pressure processing system for processing a substrate includes a first chamber, a pedestal positioned within the first chamber to support the substrate, a second chamber adjacent the first chamber, a vacuum processing system configured to lower a pressure within the second chamber to near vacuum, a valve assembly between the first chamber and the second chamber to isolate the pressure within the first chamber from the pressure within the second chamber, and a gas delivery system configured to introduce a processing gas into the first chamber and to increase the pressure within the first chamber to at least 10 atmospheres while the processing gas is in the first chamber and while the first chamber is isolated from the second chamber.

公开(公告)号：US20240306391A1

公开(公告)日：2024-09-12

申请号：US18597057

申请日：2024-03-06

Applicant: Applied Materials, Inc.

Inventor： Hao-Ling Tang ,  Arvind Kumar ,  Mahendra Pakala ,  Keith Tatseun Wong ,  Yi-Hsuan Hsiao ,  Dongqing Yang ,  Mark Conrad ,  Rio Soedibyo ,  Minrui Yu

IPC: H10B43/27 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B43/35

Abstract: Two-dimensional (2D) materials formed in very thin layers improve the operation of semiconductor devices. However, forming a contact on 2D material tends to damage and penetrate the 2D material. A relatively gentle etch process has been developed that is very selective to the 2D material and allows vertical holes to be etched down to the 2D material without damaging or penetrating the 2D material. A low-power deposition process forms a protective liner when performing the metal fill to further prevent damage to the 2D material when forming the metal contacts in the holes. These processes allow a vertical metal contact to be formed on a planar 2D material or a vertical sidewall contact be formed in a 3D NAND without damaging the 2D material. This increases the contact area, reduces the contact resistance, and improves the performance of the 2D material in the device.

公开(公告)号：US11705337B2

公开(公告)日：2023-07-18

申请号：US16696229

申请日：2019-11-26

Applicant: Applied Materials, Inc.

Inventor： Keith Tatseun Wong ,  Thomas Jongwan Kwon ,  Sean Kang ,  Ellie Y. Yieh

IPC: H01L21/285 ,  C23C16/14 ,  H10B69/00 ,  C23C16/08 ,  C23C16/56 ,  H01L21/768 ,  H10B41/20 ,  H10B43/20

CPC classification number: H01L21/28556 ,  C23C16/08 ,  C23C16/14 ,  C23C16/56 ,  H01L21/28568 ,  H01L21/76883 ,  H10B69/00 ,  H10B41/20 ,  H10B43/20

Abstract: An annealing system is provided that includes a chamber body that defines a chamber, a support to hold a workpiece and a robot to insert the workpiece into the chamber. The annealing system also includes a first gas supply to provide a hydrogen gas, a pressure source coupled to the chamber to raise a pressure in the chamber to at least 5 atmospheres, and a controller configured to cause the robot to transport a workpiece having a metal film thereon into the chamber, where the metal film contains fluorine on a surface or embedded within the metal film, to cause the first gas supply to supply the hydrogen gas to the chamber and form atomic hydrogen therein, and to cause the pressure source to raise a pressure in the chamber to at least 5 atmospheres while the workpiece is held on the support in the chamber.

公开(公告)号：US11542597B2

公开(公告)日：2023-01-03

申请号：US16902665

申请日：2020-06-16

Applicant: Applied Materials, Inc. ,  The Regents of the University of California

Inventor： Keith Tatseun Wong ,  Srinivas D. Nemani ,  Andrew C. Kummel ,  James Huang ,  Yunil Cho

IPC: C23C16/455 ,  C23C16/40 ,  C23C28/04

Abstract: Embodiments described and discussed herein provide methods for selectively depositing a metal oxides on a substrate. In one or more embodiments, methods for forming a metal oxide material includes positioning a substrate within a processing chamber, where the substrate has passivated and non-passivated surfaces, exposing the substrate to a first metal alkoxide precursor to selectively deposit a first metal oxide layer on or over the non-passivated surface, and exposing the substrate to a second metal alkoxide precursor to selectively deposit a second metal oxide layer on the first metal oxide layer. The method also includes sequentially repeating exposing the substrate to the first and second metal alkoxide precursors to produce a laminate film containing alternating layers of the first and second metal oxide layers. Each of the first and second metal alkoxide precursors contain different types of metals which are selected from titanium, zirconium, hafnium, aluminum, or lanthanum.

公开(公告)号：US20210375600A1

公开(公告)日：2021-12-02

申请号：US17333533

申请日：2021-05-28

Applicant: Applied Materials, Inc.

Inventor： Qiwei Liang ,  Srinivas D. Nemani ,  Keith Tatseun Wong ,  Antony K. Jan

IPC: H01J37/32 ,  C23C16/04 ,  H01L21/027 ,  H01L21/32

Abstract: The present disclosure generally relates to a substrate processing chamber, a substrate processing apparatus, and a substrate processing method for self-assembled monolayer (SAM) deposition of low vapor pressure organic molecules (OM) followed by further substrate processing, such as atomic layer deposition.

公开(公告)号：US10957590B2

公开(公告)日：2021-03-23

申请号：US16669082

申请日：2019-10-30

Applicant: Applied Materials, Inc.

Inventor： Wenhui Wang ,  Huixiong Dai ,  Christopher S. Ngai ,  Liqi Wu ,  Wenyu Zhang ,  Yongmei Chen ,  Hao Chen ,  Keith Tatseun Wong ,  Ke Chang

IPC: H01L21/768 ,  H01L23/535 ,  H01L21/02 ,  H01L21/033 ,  H01L21/311

Abstract: Implementations of the present disclosure generally relate to the fabrication of integrated circuits, and more particularly, to methods for forming a layer. The layer may be a mask used in lithography process to pattern and form a trench. The mask is formed over a substrate having at least two distinct materials by a selective deposition process. The edges of the mask are disposed on an intermediate layer formed on at least one of the two distinct materials. The method includes removing the intermediate layer to form a gap between edges of the mask and the substrate and filling the gap with a different material than the mask or with the same material as the mask. By filling the gap with the same or different material as the mask, electrical paths are improved.

公开(公告)号：US10916426B2

公开(公告)日：2021-02-09

申请号：US16403088

申请日：2019-05-03

Applicant: Applied Materials, Inc.

Inventor： Keith Tatseun Wong ,  Srinivas D. Nemani ,  Ellie Y. Yieh

IPC: H01L21/02 ,  C23C16/30 ,  C23C16/455 ,  C23C16/02 ,  H01L21/67 ,  C01B19/00

Abstract: Embodiments of the present disclosure relate to forming a two-dimensional crystalline dichalcogenide by positioning a substrate in an annealing apparatus. The substrate includes an amorphous film of a transition metal and a chalcogenide. The film is annealed at a temperature from 500° C. to 1200° C. In response to the annealing, a two-dimensional crystalline structure is formed from the film. The two-dimensional crystalline structure is according to a formula MX2, M includes one or more of molybdenum (Mo) or tungsten (W) and X includes one or more of sulfur (S), selenium (Se), or tellurium (Te).