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公开(公告)号：US10523194B2
公开(公告)日：2019-12-31
申请号：US15717276
申请日：2017-09-27
Applicant: Apple Inc.
Inventor： Jaroslav Raszka , Amrinder S. Barn , Victor Zyuban , Shingo Suzuki , Ajay Kumar Bhatia , Mohamed H. Abu-Rahma , Shahzad Nazar , Greg M. Hess
IPC: H03K17/16 , H03K17/14 , H03K19/00 , H03K19/003
Abstract: A power switch control circuit is disclosed. A sensor circuit may determine a leakage current of a power switch coupled to a power supply signal and a power terminal of a circuit block. The power switch may be configured to selectively couple or decouple the circuit block from the power supply signal using a switch control signal. The switch control circuit may, in response to receiving a request to open the power switch, determine a target voltage level that is greater than a voltage level of the power supply signal for the switch control signal using the leakage current, and transition the switch control signal from an initial voltage to the target voltage level.
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公开(公告)号：US20190272859A1
公开(公告)日：2019-09-05
申请号：US15912449
申请日：2018-03-05
Applicant: Apple Inc.
Inventor： Greg M. Hess , Hemangi U. Gajjewar
IPC: G11C7/12 , G11C11/419 , G11C5/14
Abstract: An apparatus is disclosed, including a plurality of memory cells, in which a given memory cell is coupled to a true bit line, a complement bit line, and a power supply signal. The apparatus also includes a pre-charge circuit that is configured to charge, for a first duration, the true bit line and the complement bit line to a voltage level that is less than a voltage level of the power supply signal. The pre-charge circuit is also configured to maintain, for a second duration that is longer than the first duration, the voltage level on the true bit line and the complement bit line.
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公开(公告)号：US20160240231A1
公开(公告)日：2016-08-18
申请号：US14624605
申请日：2015-02-18
Applicant: Apple Inc.
Inventor： Ramesh Arvapalli , Greg M. Hess
Abstract: A first plurality of storage cells may be coupled to a first pair of data lines, and a second plurality of storage cells may be coupled to a second pair of data lines. Each storage cell in the first plurality of storage cells may be configured to generate a first output signal on the first pair of data lines in response to an assertion of a respective one of first plurality of selection signals, and each storage cell in the second plurality of storage cells may be configured to generate a second output signal on the second pair of data lines in response to the assertion of a respective one of a second plurality of selection signals. Circuitry may assert a given selection signal from either the first or second plurality of selection signals. An amplifier circuit may amplify either the first or second output signal.
Abstract translation: 第一多个存储单元可以耦合到第一对数据线，并且第二多个存储单元可以耦合到第二对数据线。 第一多个存储单元中的每个存储单元可以被配置为响应于第一多个选择信号中的相应一个选择信号的断言而在第一对数据线上产生第一输出信号，并且第二多个存储单元中的每个存储单元 存储单元可以被配置为响应于第二多个选择信号中的相应一个的断言而在第二对数据线上产生第二输出信号。 电路可以从第一或第二多个选择信号中断一个给定的选择信号。 放大器电路可以放大第一或第二输出信号。
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公开(公告)号：US09311967B2
公开(公告)日：2016-04-12
申请号：US14291582
申请日：2014-05-30
Applicant: Apple Inc.
Inventor： Ajay Kumar Bhatia , Anshul Y. Mehta , Amrinder S. Barn , Greg M. Hess
CPC classification number: G11C5/147 , G11C29/021 , G11C29/028 , G11C29/52 , G11C2029/0409 , G11C2029/4402
Abstract: A system, a memory device and a method are contemplated in which the apparatus may include a plurality of memory cells, a plurality of voltage reduction circuits, and control circuitry. The plurality of voltage reduction circuits may be configured to reduce a voltage level of a power supply coupled to the plurality of memory cells. The control circuitry may be configured to select one of the voltage reduction circuits based on one or more operating parameters. The control circuitry may be further configured to activate the selected voltage reduction circuit upon receiving a write command directed towards the memory cells. The control circuitry may be further configured to execute the write command. Upon completion of the write command, the control circuitry may be further configured to de-activate the selected one of the voltage reduction circuits.
Abstract translation: 可以想到一种系统，存储器件和方法，其中该装置可以包括多个存储器单元，多个电压降低电路和控制电路。 多个电压降低电路可以被配置为降低耦合到多个存储器单元的电源的电压电平。 控制电路可以被配置为基于一个或多个操作参数来选择一个电压降低电路。 控制电路还可以被配置为在接收到针对存储器单元的写入命令时激活所选择的电压降低电路。 控制电路还可以被配置为执行写命令。 在完成写入命令之后，控制电路还可以被配置为去激活所选择的一个电压降低电路。
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公开(公告)号：US20250165404A1
公开(公告)日：2025-05-22
申请号：US19029681
申请日：2025-01-17
Applicant: Apple Inc.
Inventor： Michael R. Seningen , Ben D. Jarrett , Edward M. McCombs , Greg M. Hess
Abstract: A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmits the sparse data pattern.
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Patent Agency Ranking
公开(公告)号：US20220269617A1
公开(公告)日：2022-08-25
申请号：US17662500
申请日：2022-05-09
Applicant: Apple Inc.
Inventor： Michael R. Seningen , Ben D. Jarrett , Edward M. McCombs , Greg M. Hess
Abstract: A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmits the sparse data pattern.
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公开(公告)号：US20220101914A1
公开(公告)日：2022-03-31
申请号：US17317844
申请日：2021-05-11
Applicant: Apple Inc.
Inventor： Michael A. Dreesen , Ajay Bhatia , Michael R. Seningen , Greg M. Hess , Siddhesh Gaiki
IPC: G11C11/412 , G11C11/419 , G06F7/523
Abstract: A compute-memory circuit included in a computer system may include multiple compute data storage cells coupled to a compute bit line via respective capacitors. The compute data storage cells may store respective bits of a weight value. During a multiply operation, an operand may be used to generate a voltage level on a compute word line that is used to store respective amounts of charge on the capacitors, which are coupled to the compute bit line. The voltage on the compute bit line may be converted into multiple bits whose value is indicative of a product of the operand and the weight value.
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公开(公告)号：US20210250019A1
公开(公告)日：2021-08-12
申请号：US17245623
申请日：2021-04-30
Applicant: Apple Inc.
Inventor： Greg M. Hess , Vivekanandan Venugopal , Victor Zyuban
Abstract: A system and method for efficiently retaining data in sequential elements during power down modes. In various embodiments, a master latch of a flip-flop circuit receives an always-on first power supply voltage, whereas, a slave latch and other surrounding circuitry receives a second power supply voltage capable of being powered down. During a power down mode, circuitry consumes less power while the master latch retains stored data. In some designs, the flip-flop circuit is a level shifting circuit, and the always-on first power supply voltage is less than the second power supply voltage. The master latch uses complex gates with a p-type transistor at the top of a stack of p-type transistors receiving the always-on power supply voltage level on its source terminal and the retained data value on its gate terminal. This top p-type transistor is capable of remaining disabled even when used in a level shifting manner.
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公开(公告)号：US11005459B1
公开(公告)日：2021-05-11
申请号：US16391085
申请日：2019-04-22
Applicant: Apple Inc.
Inventor： Greg M. Hess , Vivekanandan Venugopal , Victor Zyuban
Abstract: A system and method for efficiently retaining data in sequential elements during power down modes. In various embodiments, a master latch of a flip-flop circuit receives an always-on first power supply voltage, whereas, a slave latch and other surrounding circuitry receives a second power supply voltage capable of being powered down. During a power down mode, circuitry consumes less power while the master latch retains stored data. In some designs, the flip-flop circuit is a level shifting circuit, and the always-on first power supply voltage is less than the second power supply voltage. The master latch uses complex gates with a p-type transistor at the top of a stack of p-type transistors receiving the always-on power supply voltage level on its source terminal and the retained data value on its gate terminal. This top p-type transistor is capable of remaining disabled even when used in a level shifting manner.
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公开(公告)号：US10453505B2
公开(公告)日：2019-10-22
申请号：US15912449
申请日：2018-03-05
Applicant: Apple Inc.
Inventor： Greg M. Hess , Hemangi U. Gajjewar
IPC: G11C7/00 , G11C7/12 , G11C5/14 , G11C11/419
Abstract: An apparatus is disclosed, including a plurality of memory cells, in which a given memory cell is coupled to a true bit line, a complement bit line, and a power supply signal. The apparatus also includes a pre-charge circuit that is configured to charge, for a first duration, the true bit line and the complement bit line to a voltage level that is less than a voltage level of the power supply signal. The pre-charge circuit is also configured to maintain, for a second duration that is longer than the first duration, the voltage level on the true bit line and the complement bit line.
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