公开(公告)号：US11164807B2

公开(公告)日：2021-11-02

申请号：US16563077

申请日：2019-09-06

Applicant: Advanced Micro Devices, Inc.

Inventor： John Wuu ,  Samuel Naffziger ,  Patrick J. Shyvers ,  Milind S. Bhagavat ,  Kaushik Mysore ,  Brett P. Wilkerson

IPC: H01L23/367 ,  H01L25/00 ,  H01L25/065 ,  H01L23/36 ,  H01L23/373

Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.

公开(公告)号：US20210098441A1

公开(公告)日：2021-04-01

申请号：US16586309

申请日：2019-09-27

Applicant: Advanced Micro Devices, Inc.

Inventor： John J. Wuu ,  Milind S. Bhagavat ,  Brett P. Wilkerson ,  Rahul Agarwal

IPC: H01L25/18 ,  H01L23/48 ,  H01L23/528 ,  H01L23/00

Abstract: Systems, apparatuses, and methods for routing traffic through vertically stacked semiconductor dies are disclosed. A first semiconductor die has a second die stacked vertically on top of it in a three-dimensional integrated circuit. The first die includes a through silicon via (TSV) interconnect that does not traverse the first die. The first die includes one or more metal layers above the TSV, which connect to a bonding pad interface through a bonding pad via. If the signals transferred through the TSV of the first die are shared by the second die, then the second die includes a TSV aligned with the bonding pad interface of the first die. If these signals are not shared by the second die, then the second die includes an insulated portion of a wafer backside aligned with the bonding pad interface.

公开(公告)号：US20210057352A1

公开(公告)日：2021-02-25

申请号：US16544021

申请日：2019-08-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Rahul Agarwal ,  Milind S. Bhagavat ,  Priyal Shah ,  Chia-Hao Cheng ,  Brett P. Wilkerson ,  Lei Fu

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56

Abstract: Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package is provided that includes a fan-out redistribution layer (RDL) structure that has plural stacked polymer layers, plural metallization layers, plural conductive vias interconnecting adjacent metallization layers of the metallization layers, and plural rivets configured to resist delamination of one or more of the polymer layers. Each of the plural rivets includes a first head, a second head and a shank connected between the first head and the second head. The first head is part of one of the metallization layers. The shank includes at least one of the conductive vias and at least one part of another of the metallization layers.

公开(公告)号：US20210020459A1

公开(公告)日：2021-01-21

申请号：US16513450

申请日：2019-07-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Priyal Shah ,  Milind S. Bhagavat ,  Brett P. Wilkerson ,  Lei Fu ,  Rahul Agarwal

IPC: H01L21/56 ,  H01L23/31

Abstract: Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package includes a package substrate that has a first side and a second side opposite to the first side. A semiconductor chip is mounted on the first side. Plural metal anchor structures are coupled to the package substrate and project away from the first side. A molding layer is on the package substrate and at least partially encapsulates the semiconductor chip and the anchor structures. The anchor structures terminate in the molding layer and anchor the molding layer to the package substrate.

公开(公告)号：US10573630B2

公开(公告)日：2020-02-25

申请号：US15958169

申请日：2018-04-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Brett P. Wilkerson ,  Milind Bhagavat ,  Rahul Agarwal ,  Dmitri Yudanov

IPC: H01L25/18 ,  H01L23/367 ,  H01L23/00 ,  H01L25/00 ,  H01L23/48

Abstract: A three-dimensional integrated circuit includes a first die having a first geometry. The first die includes a first region that operates with a first power density and a second region that operates with a second power density. The first power density is less than the second power density. The first die includes first electrical contacts disposed in the first region on a first side of the first die along a periphery of the first die. The three-dimensional integrated circuit includes a second die having a second geometry. The second die includes second electrical contacts disposed on a first side of the second die. A stacked portion of the second die is stacked within the periphery of the first die and an overhang portion of the second die extends beyond the periphery of the first die. The second electrical contacts are aligned with and coupled to the first electrical contacts.

公开(公告)号：US12276850B2

公开(公告)日：2025-04-15

申请号：US18357376

申请日：2023-07-24

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Brett P. Wilkerson ,  Raja Swaminathan ,  Kong Toon Ng ,  Rahul Agarwal

IPC: G02B6/42 ,  G02B6/43

Abstract: A semiconductor package includes a first mold layer at least partially encasing at least one photonic integrated circuit. A redistribution layer structure is fabricated on the first mold layer, the redistribution layer structure including dielectric material and conductive structures. A second mold layer at least partially encasing at least one semiconductor chip is fabricated on the redistribution layer structure. The redistribution layer structure provides electrical pathways between the at least one semiconductor chip and the at least one photonic integrated circuit. One or more voids are defined in the second mold layer in an area above an optical interface of the at least one photonic integrated circuit such that light is transmittable through dielectric material above the optical interface.

公开(公告)号：US12107075B2

公开(公告)日：2024-10-01

申请号：US18324744

申请日：2023-05-26

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Lei Fu ,  Brett P. Wilkerson ,  Rahul Agarwal

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L25/0655 ,  H01L23/5381 ,  H01L23/5389 ,  H01L24/13 ,  H01L2225/06541

Abstract: A chip for hybrid bonded interconnect bridging for chiplet integration, the chip comprising: a first chiplet; a second chiplet; an interconnecting die coupled to the first chiplet and the second chiplet through a hybrid bond.

公开(公告)号：US20240047228A1

公开(公告)日：2024-02-08

申请号：US17816944

申请日：2022-08-02

Applicant: Advanced Micro Devices, Inc.

Inventor： Sri Ranga Sai Boyapati ,  Deepak Vasant Kulkarni ,  Raja Swaminathan ,  Brett P. Wilkerson ,  Arsalan Alam

IPC: H01L21/48 ,  H01L23/64 ,  H01L23/498

CPC classification number: H01L21/486 ,  H01L21/4857 ,  H01L23/642 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894

Abstract: A disclosed method can include (i) positioning a first surface of a component of a semiconductor device on a first plated through-hole, (ii) covering, with a layer of dielectric material, at least a second surface of the component that is opposite the first surface of the component, (iii) removing a portion of the layer of dielectric material covering the second surface of the component to form at least one cavity, and (iv) depositing conductive material in the cavity to form a second plated through-hole on the second surface of the component. Various other apparatuses, systems, and methods are also disclosed.

公开(公告)号：US11709327B2

公开(公告)日：2023-07-25

申请号：US17361033

申请日：2021-06-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Brett P. Wilkerson ,  Raja Swaminathan ,  Kong Toon Ng ,  Rahul Agarwal

IPC: G02B6/42 ,  G02B6/43

CPC classification number: G02B6/4274 ,  G02B6/425 ,  G02B6/4255 ,  G02B6/43

Abstract: A semiconductor package includes a first mold layer at least partially encasing at least one photonic integrated circuit. A redistribution layer structure is fabricated on the first mold layer, the redistribution layer structure including dielectric material and conductive structures. A second mold layer at least partially encasing at least one semiconductor chip is fabricated on the redistribution layer structure. The redistribution layer structure provides electrical pathways between the at least one semiconductor chip and the at least one photonic integrated circuit. One or more voids are defined in the second mold layer in an area above an optical interface of the at least one photonic integrated circuit such that light is transmittable through dielectric material above the optical interface.

公开(公告)号：US20230207544A1

公开(公告)日：2023-06-29

申请号：US17560691

申请日：2021-12-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Gabriel H. Loh ,  Rahul Agarwal ,  Raja Swaminathan ,  Brett P. Wilkerson

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L21/768

CPC classification number: H01L25/18 ,  H01L24/16 ,  H01L25/50 ,  H01L21/76898 ,  H01L2224/16145 ,  H01L2224/16225

Abstract: A semiconductor device includes one or more active devices disposed between a processor die and a package substrate. The semiconductor device includes a first layer with a processor die, a second layer with one or more active devices, and a third layer with a package substrate, where the second layer is disposed between the first and third layers. The one or more active devices are semiconductor-based devices, such as voltage regulators, that participate in supplying power to the processor die and are electrically connected to the processor die using various connection configurations. The implementations use short path lengths for improved performance with a compact structure that avoids the use of edge wiring or interposers without occupying processor die space. Implementations include the use of through-silicon vias (TSVs) to provide short path lengths while reducing the number of connection resources used by the one or more power components.