公开(公告)号：US20250029900A1

公开(公告)日：2025-01-23

申请号：US18784143

申请日：2024-07-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Deepak Vasant Kulkarni ,  Rahul Agarwal ,  Rajasekaran Swaminathan ,  Chintan Buch

IPC: H01L23/495 ,  H01L23/14 ,  H10B12/00

Abstract: Apparatuses, systems and methods for efficiently generating a package substrate. A semiconductor fabrication process (or process) fabricates each of a first glass package substrate and a second glass package substrate with a redistribution layer on a single side of a respective glass wafer. The process flips the second glass package substrate upside down and connects the glass wafers of the first and second glass package substrates together using a wafer bonding technique. In some implementations, the process uses copper-based wafer bonding. The resulting bonding between the two glass wafers contains no air gap, no underfill, and no solder bumps. Afterward, the side of the first glass package substrate opposite the glass wafer is connected to at least one integrated circuit. Additionally, the side of the second glass package substrate opposite the glass wafer is connected to a component on the motherboard through pads on the motherboard.

公开(公告)号：US12080632B2

公开(公告)日：2024-09-03

申请号：US17489182

申请日：2021-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Deepak Vasant Kulkarni ,  Rahul Agarwal ,  Rajasekaran Swaminathan ,  Chintan Buch

IPC: H01L23/495 ,  H01L23/14 ,  H10B12/00

CPC classification number: H01L23/4951 ,  H01L23/145 ,  H10B12/50

Abstract: Apparatuses, systems and methods for efficiently generating a package substrate. A semiconductor fabrication process (or process) fabricates each of a first glass package substrate and a second glass package substrate with a redistribution layer on a single side of a respective glass wafer. The process flips the second glass package substrate upside down and connects the glass wafers of the first and second glass package substrates together using a wafer bonding technique. In some implementations, the process uses copper-based wafer bonding. The resulting bonding between the two glass wafers contains no air gap, no underfill, and no solder bumps. Afterward, the side of the first glass package substrate opposite the glass wafer is connected to at least one integrated circuit. Additionally, the side of the second glass package substrate opposite the glass wafer is connected to a component on the motherboard through pads on the motherboard.

公开(公告)号：US20230102183A1

公开(公告)日：2023-03-30

申请号：US17489182

申请日：2021-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Deepak Vasant Kulkarni ,  Rahul Agarwal ,  Rajasekaran Swaminathan ,  Chintan Buch

IPC: H01L23/495 ,  H01L23/14

Abstract: Apparatuses, systems and methods for efficiently generating a package substrate. A semiconductor fabrication process (or process) fabricates each of a first glass package substrate and a second glass package substrate with a redistribution layer on a single side of a respective glass wafer. The process flips the second glass package substrate upside down and connects the glass wafers of the first and second glass package substrates together using a wafer bonding technique. In some implementations, the process uses copper-based wafer bonding. The resulting bonding between the two glass wafers contains no air gap, no underfill, and no solder bumps. Afterward, the side of the first glass package substrate opposite the glass wafer is connected to at least one integrated circuit. Additionally, the side of the second glass package substrate opposite the glass wafer is connected to a component on the motherboard through pads on the motherboard.

公开(公告)号：US20240006290A1

公开(公告)日：2024-01-04

申请号：US17854907

申请日：2022-06-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Sriranga Sai Boyapati ,  Deepak Vasant Kulkarni ,  Rajasekaran Swaminathan

IPC: H01L23/498 ,  H01L23/64 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L23/642 ,  H01L23/645 ,  H01L21/4857 ,  H01L2224/73204 ,  H01L24/73

Abstract: An apparatus and method for efficiently transferring information as signals through a silicon package substrate. A semiconductor fabrication process (or process) begins with a relatively thin package substrate core layer and uses lasers to create openings in the package substrate at locations of the signal routes. The use of each of the relatively thin core layer and the lasers allows for reduction in the pitch of the signal routes. The process creates signal routes in the openings using stacked vias from one side of the package substrate to an opposite side of the package substrate. Additionally, the process forms the package substrate with multiple embedded passive components with different thicknesses in different layers of the package substrate. The embedded passive components are used to improve signal integrity of the signal routes.

公开(公告)号：US20240212908A1

公开(公告)日：2024-06-27

申请号：US18478416

申请日：2023-09-29

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Robert Grant Spurney ,  Alexander Helmut Pfeiffenberger ,  Sri Ranga Sai Boyapati ,  Deepak Vasant Kulkarni

IPC: H01F17/00 ,  H01F17/04 ,  H01F27/255

CPC classification number: H01F17/0013 ,  H01F17/04 ,  H01F27/255 ,  H01F2017/002 ,  H01F2017/048

Abstract: The disclosed inductor includes a magnetic material surrounding a conductive core. The magnetic material and conductive core can be embedded in a substrate. The magnetic material and conductive core can be formed in the substrate, using a magnetic composite material. Various other systems and methods are also disclosed.

公开(公告)号：US20240047228A1

公开(公告)日：2024-02-08

申请号：US17816944

申请日：2022-08-02

Applicant: Advanced Micro Devices, Inc.

Inventor： Sri Ranga Sai Boyapati ,  Deepak Vasant Kulkarni ,  Raja Swaminathan ,  Brett P. Wilkerson ,  Arsalan Alam

IPC: H01L21/48 ,  H01L23/64 ,  H01L23/498

CPC classification number: H01L21/486 ,  H01L21/4857 ,  H01L23/642 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894

Abstract: A disclosed method can include (i) positioning a first surface of a component of a semiconductor device on a first plated through-hole, (ii) covering, with a layer of dielectric material, at least a second surface of the component that is opposite the first surface of the component, (iii) removing a portion of the layer of dielectric material covering the second surface of the component to form at least one cavity, and (iv) depositing conductive material in the cavity to form a second plated through-hole on the second surface of the component. Various other apparatuses, systems, and methods are also disclosed.