公开(公告)号：US20240274549A1

公开(公告)日：2024-08-15

申请号：US18169788

申请日：2023-02-15

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Alexander Helmut Pfeiffenberger ,  Robert Grant Spurney ,  Sriranga Sai Boyapati

IPC: H01L23/64 ,  H01F17/00 ,  H01F17/04 ,  H01L23/14 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/645 ,  H01F17/0013 ,  H01F17/04 ,  H01L23/145 ,  H01L23/49822 ,  H01L23/49838 ,  H01L25/0655 ,  H01F2017/002 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/1427 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/14335

Abstract: An apparatus and method for efficient power management of multiple integrated circuits. An apparatus includes an integrated circuit and a package substrate that includes an embedded inductor. The package substrate includes a glass-reinforced epoxy laminate material. The embedded inductor is formed within a cavity of the package substrate, and includes two negatively coupled inductors connected in a parallel combination. The embedded inductor receives an output voltage generated by a voltage regulator, and conveys this output voltage to a power supply input pin of the integrated circuit. Each of the two negatively coupled inductors utilizes a ferrite core. During a transient voltage condition of the output voltage generated by the voltage regulator, the embedded inductor provides an inductance that is less than an inductance it provides for a steady-state voltage condition of the output voltage generated by the voltage regulator.

公开(公告)号：US20240006290A1

公开(公告)日：2024-01-04

申请号：US17854907

申请日：2022-06-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Sriranga Sai Boyapati ,  Deepak Vasant Kulkarni ,  Rajasekaran Swaminathan

IPC: H01L23/498 ,  H01L23/64 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L23/642 ,  H01L23/645 ,  H01L21/4857 ,  H01L2224/73204 ,  H01L24/73

Abstract: An apparatus and method for efficiently transferring information as signals through a silicon package substrate. A semiconductor fabrication process (or process) begins with a relatively thin package substrate core layer and uses lasers to create openings in the package substrate at locations of the signal routes. The use of each of the relatively thin core layer and the lasers allows for reduction in the pitch of the signal routes. The process creates signal routes in the openings using stacked vias from one side of the package substrate to an opposite side of the package substrate. Additionally, the process forms the package substrate with multiple embedded passive components with different thicknesses in different layers of the package substrate. The embedded passive components are used to improve signal integrity of the signal routes.