Invention Grant
- Patent Title: Offset-aligned three-dimensional integrated circuit
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Application No.: US15958169Application Date: 2018-04-20
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Publication No.: US10573630B2Publication Date: 2020-02-25
- Inventor: Brett P. Wilkerson , Milind Bhagavat , Rahul Agarwal , Dmitri Yudanov
- Applicant: Advanced Micro Devices, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Zagorin Cave LLP
- Main IPC: H01L25/18
- IPC: H01L25/18 ; H01L23/367 ; H01L23/00 ; H01L25/00 ; H01L23/48

Abstract:
A three-dimensional integrated circuit includes a first die having a first geometry. The first die includes a first region that operates with a first power density and a second region that operates with a second power density. The first power density is less than the second power density. The first die includes first electrical contacts disposed in the first region on a first side of the first die along a periphery of the first die. The three-dimensional integrated circuit includes a second die having a second geometry. The second die includes second electrical contacts disposed on a first side of the second die. A stacked portion of the second die is stacked within the periphery of the first die and an overhang portion of the second die extends beyond the periphery of the first die. The second electrical contacts are aligned with and coupled to the first electrical contacts.
Public/Granted literature
- US20190326272A1 OFFSET-ALIGNED THREE-DIMENSIONAL INTEGRATED CIRCUIT Public/Granted day:2019-10-24
Information query
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