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公开(公告)号：US20180074743A1
公开(公告)日：2018-03-15
申请号：US15263833
申请日：2016-09-13
Applicant: Apple Inc.
Inventor： Robert E. Jeter , Liang Deng , Kai Lun Hsiung , Manu Gulati , Rakesh L. Notani , Sukalpa Biswas , Venkata Ramana Malladi , Gregory S. Mathews , Enming Zheng , Fabien S. Faure
CPC classification number: G06F3/0634 , G06F1/08 , G06F1/324 , G06F3/0625 , G06F3/0653 , G06F3/0659 , G06F3/0673 , G06F3/0683 , G06F13/1689 , G06F13/4243 , Y02D10/14 , Y02D10/151
Abstract: Systems, apparatuses, and methods for improved memory controller power management techniques. An apparatus includes control logic, one or more memory controller(s), and one or more memory devices. If the amount of traffic and/or queue depth for a given memory controller falls below a threshold, the clock frequency supplied to the given memory controller and corresponding memory device(s) is reduced. In one embodiment, the clock frequency is reduced by one half If the amount of traffic and/or queue depth rises above the threshold, then the clock frequency is increased back to its original frequency. The clock frequency may be adjusted by doubling the divisor used by a clock divider, which enables fast switching between the original rate and the reduced rate. This in turn allows for more frequent switching between the low power and normal power states, resulting in the memory controller and memory device operating more efficiently.
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公开(公告)号：US09829966B2
公开(公告)日：2017-11-28
申请号：US14486491
申请日：2014-09-15
Applicant: Apple Inc.
Inventor： Manu Gulati , Tristan R. Hudson , Parin Patel , Fabien Faure
CPC classification number: G06F1/3296 , G06F1/206 , G06F1/30 , G06F1/3275 , Y02D10/14 , Y02D10/16 , Y02D10/172
Abstract: In an embodiment, a system includes a power management unit (PMU), a non-volatile memory, a volatile memory, and a processor. The PMU may be configured to generate a power supply voltage, change a state of a status signal responsive to an event, and reduce a voltage level of the power supply voltage responsive to a predetermined period of time elapsing from detecting the event. The system may be configured to transition from a first to a second operating mode responsive to the change of the state of the status signal, and cancel pending commands to the non-volatile memory responsive to the transition to the second operating mode. The non-volatile memory may be configured to complete active commands prior the predetermined period of time elapsing.
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公开(公告)号：US20170213557A1
公开(公告)日：2017-07-27
申请号：US15482142
申请日：2017-04-07
Applicant: Apple Inc.
Inventor： Manu Gulati , Gilbert H. Herbeck , Alexei E. Kosut , Girault W. Jones , Timothy J. Millet
CPC classification number: G10L15/28 , G10L15/08 , G10L15/22 , G10L2015/088 , G10L2015/223
Abstract: In an embodiment, a system on a chip (SOC) may include one or more central processing units (CPUs), a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples and match those audio samples against a predetermined pattern. The circuit may operate according to a first clock during the time that the rest of the SOC is powered down. In response to detecting the predetermined pattern in the samples, the circuit may cause the memory controller and processors to power up. During the power up process, a second clock having one or more better characteristics than the first clock may become available. The circuit may switch to the second clock while preserving the samples, or losing at most one sample, or no more than a threshold number of samples.
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公开(公告)号：US20170091026A1
公开(公告)日：2017-03-30
申请号：US15273208
申请日：2016-09-22
Applicant: Apple Inc.
Inventor： Manu Gulati , Sukalpa Biswas , Jeffrey R. Wilcox , Farid Nemati
CPC classification number: G06F11/1068 , G06F12/0669 , G06F12/1072 , G06F12/12 , G06F12/121 , G06F12/126 , G06F2212/1032 , G06F2212/7204 , G06F2212/7207 , G11C29/52 , G11C29/70 , G11C29/72 , G11C2029/0409 , G11C2029/0411 , G11C2029/4402
Abstract: In one embodiment, a system includes a memory that includes a live section and a spares section. The live section may be mapped to the address space of the system, and may be accessed in response to memory operations. Once an entry in the live section has been detected as failed, an entry is in the spares section may be allocated to replace the failed entry. During subsequent accesses to the failed entry, the allocated entry may be used instead. In an embodiment, the failed entry may be coded with an indication of the allocated entry, to redirect to the allocated entry. In one implementation, for example, the failed entry may be coded with N copies of a pointer to the allocated entry, each copy protected by corresponding ECC.
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公开(公告)号：US20170039672A1
公开(公告)日：2017-02-09
申请号：US14816508
申请日：2015-08-03
Applicant: Apple Inc.
Inventor： Timothy J. Millet , Manu Gulati , Arthur L. Spence , Gurjeet S. Saund , Robert P. Esser
CPC classification number: G06T1/20 , G06F9/4893 , G06F9/52 , G06T1/60 , G09G5/001 , G09G5/363 , G09G2360/08 , Y02D10/24
Abstract: An embodiment of a system may include a plurality of media units, a processor, and circuitry. Each media unit may be configured to execute one or more commands to process a display image. The processor may be configured to store a plurality of media processing commands in a queue. The circuitry may be configured to retrieve a first media processing command from the queue and send the first media processing command to a first media unit. The circuitry may also be configured to retrieve a second media processing from the queue and send the second media processing command to a second media unit in response to receiving an interrupt from the first media unit. The circuitry may then copy data from the first media unit to the second media unit in response to receiving the interrupt from the first media unit.
Abstract translation: 系统的实施例可以包括多个媒体单元，处理器和电路。 每个媒体单元可以被配置为执行一个或多个命令来处理显示图像。 处理器可以被配置为在队列中存储多个媒体处理命令。 电路可以被配置为从队列检索第一媒体处理命令，并将第一媒体处理命令发送到第一媒体单元。 电路还可以被配置为响应于从第一媒体单元接收到中断而从队列中检索第二媒体处理并将第二媒体处理命令发送到第二媒体单元。 响应于接收到来自第一媒体单元的中断，电路可以将数据从第一媒体单元复制到第二媒体单元。
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Patent Agency Ranking
公开(公告)号：US20140122759A1
公开(公告)日：2014-05-01
申请号：US13666132
申请日：2012-11-01
Applicant: APPLE INC.
Inventor： Erik P. Machnicki , Deniz Balkan , Manu Gulati
IPC: G06F13/24
CPC classification number: G06F13/24
Abstract: In an embodiment, a system includes an interrupt controller, one or more CPUs coupled to the interrupt controller, a communication fabric, one or more peripheral devices configured to generate interrupts to be transmitted to the interrupt controller, and one or more interrupt message circuits coupled to the peripheral devices. The interrupt message circuits are configured to generate interrupt messages to convey the interrupts over the fabric to the interrupt controller. Some of the interrupts are level-sensitive interrupts, and the interrupt message circuits are configured to transmit level-sensitive interrupt messages to the interrupt controller. At least one of the interrupts is edge-triggered. The system is configured to convert the edge-triggered interrupt to a level-sensitive interrupt so that interrupts may be handled in the same fashion.
Abstract translation: 在一个实施例中，系统包括中断控制器，耦合到中断控制器的一个或多个CPU，通信结构，被配置为产生要发送到中断控制器的中断的一个或多个外围设备，以及一个或多个中断消息电路耦合 到外围设备。 中断消息电路被配置为产生中断消息，以将中断通过结构传送到中断控制器。 一些中断是电平敏感中断，并且中断消息电路被配置为向中断控制器发送电平敏感中断消息。 至少有一个中断是边沿触发的。 该系统配置为将边沿触发中断转换为电平敏感中断，以便可以以相同的方式处理中断。
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公开(公告)号：US11714924B2
公开(公告)日：2023-08-01
申请号：US17469591
申请日：2021-09-08
Applicant: Apple Inc.
Inventor： Manu Gulati , Joseph Sokol, Jr. , Jeffrey R. Wilcox , Bernard J. Semeria , Michael J. Smith
CPC classification number: G06F21/72 , G06F12/0246 , G06F12/1027 , G06F12/1408 , G06F21/78 , H04L9/0861 , H04L9/0894 , G06F2212/7206 , G06F2212/7208 , G06F2221/2143 , H04L2209/12
Abstract: In one embodiment, a system includes a non-volatile memory that may serve as both the main memory system and the backing store (or persistent storage). In some embodiments, the non-volatile memory is divided into a main memory portion and a persistent portion. Data in the main memory operation may be encrypted using one or more first keys, and data in the persistent portion may be encrypted using one or more second keys, in an embodiment. The volatile behavior of main memory may be implemented by discarding the one or more first keys in a power down event or other event that indicates a loss of main memory data, while the one or more second keys may be retained. In one embodiment, the physical address space of the non-volatile memory may be a mapping from a second physical address space that is used within the system.
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公开(公告)号：US20200257829A1
公开(公告)日：2020-08-13
申请号：US16859634
申请日：2020-04-27
Applicant: Apple Inc.
Inventor： Manu Gulati , Joseph Sokol, Jr. , Jeffrey R. Wilcox , Bernard J. Semeria , Michael J. Smith
Abstract: In one embodiment, a system includes a non-volatile memory that may serve as both the main memory system and the backing store (or persistent storage). In some embodiments, the non-volatile memory is divided into a main memory portion and a persistent portion. Data in the main memory operation may be encrypted using one or more first keys, and data in the persistent portion may be encrypted using one or more second keys, in an embodiment. The volatile behavior of main memory may be implemented by discarding the one or more first keys in a power down event or other event that indicates a loss of main memory data, while the one or more second keys may be retained. In one embodiment, the physical address space of the non-volatile memory may be a mapping from a second physical address space that is used within the system.
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公开(公告)号：US10573319B2
公开(公告)日：2020-02-25
申请号：US16546574
申请日：2019-08-21
Applicant: Apple Inc. , Diane Culbert
Inventor： Timothy J. Millet , Manu Gulati , Michael F. Culbert
IPC: G10L15/22 , G10L15/28 , G06F1/3228 , G06F1/3287 , G06F1/32 , G06F3/16 , G10L25/48 , G10L15/08
Abstract: In an embodiment, an integrated circuit may include one or more CPUs, a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples from a microphone, and match those audio samples against a predetermined pattern to detect a possible command from a user of the device that includes the SOC. In response to detecting the predetermined pattern, the circuit may cause the memory controller to power up so that audio samples may be stored in the memory to which the memory controller is coupled. The circuit may also cause the CPUs to be powered on and initialized, and the operating system (OS) may boot. During the time that the CPUs are initializing and the OS is booting, the circuit and the memory may be capturing the audio samples.
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公开(公告)号：US20190287532A1
公开(公告)日：2019-09-19
申请号：US16397057
申请日：2019-04-29
Applicant: Apple Inc.
Inventor： Timothy J. Millet , Manu Gulati , Michael F. Culbert
IPC: G10L15/28 , G06F1/3287 , G06F1/3228 , G06F3/16 , G10L15/22 , G06F1/32
Abstract: In an embodiment, an integrated circuit may include one or more CPUs, a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples from a microphone, and match those audio samples against a predetermined pattern to detect a possible command from a user of the device that includes the SOC. In response to detecting the predetermined pattern, the circuit may cause the memory controller to power up so that audio samples may be stored in the memory to which the memory controller is coupled. The circuit may also cause the CPUs to be powered on and initialized, and the operating system (OS) may boot. During the time that the CPUs are initializing and the OS is booting, the circuit and the memory may be capturing the audio samples.
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