公开(公告)号：US20190042336A1

公开(公告)日：2019-02-07

申请号：US15840473

申请日：2017-12-13

Applicant: Apple Inc.

Inventor： Jason McElrath ,  Karan Sanghi ,  Saurabh Garg

IPC: G06F9/54 ,  G06F13/362

Abstract: Methods and apparatus for scheduling time sensitive operations among independent processors. In one embodiment, an application processor (AP) determines transmission timing parameters for a baseband processor (BB). Thereafter, the AP can generate and transact generic time-sensitive RTP data with the BB in time for transmission via a Long Term Evolution (LTE) communication stack. In this manner, the AP's scheduler can coordinate/accommodate digital audio tasks within the context of its other tasks (e.g., to enable intelligent sleep and wake-up operation, load balancing, memory usage, and/or any number of other processor management functions).

公开(公告)号：US10198364B2

公开(公告)日：2019-02-05

申请号：US15271102

申请日：2016-09-20

Applicant: Apple Inc.

Inventor： Saurabh Garg ,  Karan Sanghi ,  Vladislav Petkov ,  Haining Zhang

IPC: G06F12/00 ,  G06F12/14 ,  G06F12/1081

Abstract: Methods and apparatus for registering and handling access violations of host memory. In one embodiment, a peripheral processor receives one or more window registers defining an extent of address space accessible from a host processor; responsive to an attempt to access an extent of address space outside of the extent of accessible address space, generates an error message; stores the error message within a violation register; and resumes operation of the peripheral processor upon clearance of the stored error message.

公开(公告)号：US09830289B2

公开(公告)日：2017-11-28

申请号：US14856283

申请日：2015-09-16

Applicant: Apple Inc.

Inventor： Radha Kumar Pulyala ,  Saurabh Garg ,  Karan Sanghi

IPC: G06F13/28 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/287 ,  G06F13/4022 ,  G06F13/4282

Abstract: Methods and apparatus for data aggregation and multiplexing of one or more virtual bus interfaces via a physical bus interface. Various disclosed embodiments are configured to: (i) multiplex multiple logical interfaces over a single physical interface, (ii) exchange session management and logical interface control, (iii) manage flow control, (iv) provide “hints” about the data (e.g., metadata), and/or (v) pad data packets. In one particular implementation, the methods and apparatus are configured for use within a wireless-enabled portable electronic device, such as for example a cellular-enabled smartphone, and make use of one or more features of a high-speed serialized physical bus interface.

公开(公告)号：US11368560B2

公开(公告)日：2022-06-21

申请号：US16368214

申请日：2019-03-28

Applicant: Apple Inc.

Inventor： Cahya Adiansyah Masputra ,  Karan Sanghi ,  Mingzhe Zhang ,  Jason McElrath ,  Sandeep Nair

IPC: G06F7/02 ,  H04L69/16 ,  H04L69/163 ,  H04L69/164 ,  H04L12/46 ,  G06F9/54 ,  H04L9/40 ,  G06F9/48 ,  G06F9/50 ,  G06F12/10 ,  G06F13/16 ,  G06F3/06 ,  G06F9/46 ,  G06F12/02 ,  H04L47/2475 ,  H04L47/2483 ,  H04L47/6295 ,  H04L49/00 ,  H04L49/9047 ,  H04L69/00 ,  G06F9/455 ,  H04L47/193 ,  H04L47/283 ,  G06F9/52 ,  H04L43/0864 ,  G06F16/23 ,  G06F21/52 ,  H04L47/24 ,  H04L47/30 ,  H04L47/32 ,  H04L47/6275 ,  G06F21/56 ,  H04L69/22 ,  G06F16/22 ,  H04L61/103 ,  H04L61/2503 ,  H04L67/146 ,  H04L69/18 ,  H04L1/00

Abstract: Methods and apparatus for efficient data transfer within a user space network stack. Unlike prior art monolithic networking stacks, the exemplary networking stack architecture described hereinafter includes various components that span multiple domains (both in-kernel, and non-kernel). For example, unlike traditional “socket” based communication, disclosed embodiments can transfer data directly between the kernel and user space domains. Direct transfer reduces the per-byte and per-packet costs relative to socket based communication. A user space networking stack is disclosed that enables extensible, cross-platform-capable, user space control of the networking protocol stack functionality. The user space networking stack facilitates tighter integration between the protocol layers (including TLS) and the application or daemon. Exemplary systems can support multiple networking protocol stack instances (including an in-kernel traditional network stack).

公开(公告)号：US11243560B2

公开(公告)日：2022-02-08

申请号：US17066321

申请日：2020-10-08

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Saurabh Garg

IPC: G06F1/12 ,  G06F1/32 ,  G06F1/324

Abstract: Methods and apparatus for synchronization of time between independently operable processors. Time synchronization between independently operable processors is complicated by a variety of factors. For example, neither independently operable processor controls the other processor's task scheduling, power, or clocking. In one exemplary embodiment, a processor can initiates a time synchronization process by disabling power state machines and transacting timestamps for a commonly observed event. In one such embodiment, timestamps may be transferred via inter-processor communication (IPC) mechanisms (e.g., transfer descriptors (TDs), and completion descriptors (CDs)). Both processors may thereafter coordinate in time synchronization efforts (e.g., speeding up or slowing down their respective clocks, etc.).

公开(公告)号：US10719376B2

公开(公告)日：2020-07-21

申请号：US16112383

申请日：2018-08-24

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Saurabh Garg

IPC: G06F3/00 ,  G06F9/44 ,  G06F9/46 ,  G06F13/00 ,  G06F9/54 ,  G06F15/173 ,  G06F9/38

Abstract: Methods and apparatus for transacting multiple data flows between multiple processors. In one such implementation, multiple data pipes are aggregated over a common transfer data structure. Completion status information corresponding to each data pipe is provided over individual completion data structures. Allocating a common fixed pool of resources for data transfer can be used in a variety of different load balancing and/or prioritization schemes; however, individualized completion status allows for individualized data pipe reclamation. Unlike prior art solutions which dynamically created and pre-allocated memory space for each data pipe individually, the disclosed embodiments can only request resources from a fixed pool. In other words, outstanding requests are queued (rather than immediately serviced with a new memory allocation), thus overall bandwidth remains constrained regardless of the number of data pipes that are opened and/or closed.

公开(公告)号：US10558580B2

公开(公告)日：2020-02-11

申请号：US15273398

申请日：2016-09-22

Applicant: Apple Inc.

Inventor： Vladislav Petkov ,  Haining Zhang ,  Karan Sanghi ,  Saurabh Garg

IPC: G06F12/1009 ,  G06F3/06 ,  G06F8/61 ,  G06F13/42 ,  G06F1/24 ,  G06F12/14

Abstract: Methods and apparatus for enabling a peripheral processor to retrieve and load firmware for execution within the constraints of its memory. The peripheral processor is allocated a portion of the host processor's memory, to function as a logical secondary and tertiary memory for memory cache operation. The described embodiments enable the peripheral processor to support much larger and more complex firmware. Additionally, a multi-facetted locking mechanism is described which enables the peripheral processor and the host processor to access the secondary memory, while minimally impacting the other processor.

公开(公告)号：US20190342225A1

公开(公告)日：2019-11-07

申请号：US15973153

申请日：2018-05-07

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Saurabh Garg ,  Cahya Adiansyah Masputra

IPC: H04L12/863 ,  H04L12/725

Abstract: Methods and apparatus for non-sequential packet transfer. Prior art multi-processor devices implement a complete network communications stack at each processor. The disclosed embodiments provide techniques for delivering network layer (L3) and/or transport layer (L4) data payloads in the order of receipt, rather than according to the data link layer (L2) order. The described techniques enable e.g., earlier packet delivery. Such design topologies can operate within a substantially smaller memory footprint compared to prior art solutions. As a related benefit, applications that are unaffected by data link layer corruptions can receive data immediately (rather than waiting for the re-transmission of an unrelated L4 data flow) and thus the overall network latency can be greatly reduced and user experience can be improved.

公开(公告)号：US10346226B2

公开(公告)日：2019-07-09

申请号：US15720603

申请日：2017-09-29

Applicant: Apple Inc.

Inventor： Jason McElrath ,  Karan Sanghi ,  Saurabh Garg

IPC: G06F13/42 ,  G06F13/16 ,  G06F9/46 ,  G06F9/54 ,  G06F13/362 ,  H04W84/04 ,  H04W72/12

Abstract: Methods and apparatus for time sensitive data transfer between logical domains. In one embodiment, an user equipment (UE) device has an application processor (AP) coupled to a baseband processor (BB) that operate independently of one another normally, but may cooperate in limited hybrid use scenarios. For example, the BB receives audio packets via a cellular network that are converted to pulse code modulated (PCM) digital audio to be played by the AP. Unfortunately, since the AP and the BB are independently clocked, they will experience some clock drift. As a result, the audio playback may have undesirable artifacts if the drift is not otherwise compensated for. To these ends, the AP and/or BB determine a relative clock drift and compensate for playback by e.g., adding, padding, or deleting audio samples and/or audio packets. Techniques for handover scenarios are also disclosed.

公开(公告)号：US20190034368A1

公开(公告)日：2019-01-31

申请号：US16056374

申请日：2018-08-06

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Vladislav Petkov ,  Radha Kumar Pulyala ,  Saurabh Garg ,  Haining Zhang

IPC: G06F13/28 ,  G06F13/40

CPC classification number: G06F13/28 ,  G06F13/4027 ,  Y02D10/14 ,  Y02D10/151

Abstract: Methods and apparatus for a synchronized multi-directional transfer on an inter-processor communication (IPC) link. In one embodiment, the synchronized multi-directional transfer utilizes one or more buffers which are configured to accumulate data during a first state. The one or more buffers are further configured to transfer the accumulated data during a second state. Data is accumulated during a low power state where one or more processors are inactive, and the data transfer occurs during an operational state where the processors are active. Additionally, in some variants, the data transfer may be performed for currently available transfer resources, and halted until additional transfer resources are made available. In still other variants, one or more of the independently operable processors may execute traffic monitoring processes so as to optimize data throughput of the IPC link.