公开(公告)号：US20080185738A1

公开(公告)日：2008-08-07

申请号：US12016677

申请日：2008-01-18

Applicant: Jae Sik CHUNG ,  Sung Min SIM ,  Hee Kook CHOI ,  Dong Hyeon JANG

Inventor： Jae Sik CHUNG ,  Sung Min SIM ,  Hee Kook CHOI ,  Dong Hyeon JANG

IPC: H01L23/52 ,  H01L21/44

CPC classification number: H01L23/525 ,  H01L21/7682 ,  H01L23/3114 ,  H01L23/5222 ,  H01L24/06 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/02311 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06136 ,  H01L2224/11901 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device and a method for fabricating the same are disclosed. According to some embodiments, a semiconductor device comprises a lower structure formed on a semiconductor structure. The lower structure has chip pads. The semiconductor device further comprises a passivation layer located over the chip pads. The passivation layer comprises first openings defined therein to expose at least a portion of the chip pads. The semiconductor device additionally includes at least two adjacent redistribution lines spaced apart from each other and located over the passivation layer. The at least two redistribution lines are respectively coupled to the chip pads through corresponding ones of the first openings. The semiconductor device comprises a first insulation layer located over the passivation layer. The first insulation layer includes a void extending between the at least two adjacent redistribution lines.

Abstract translation: 公开了一种半导体器件及其制造方法。 根据一些实施例，半导体器件包括形成在半导体结构上的下部结构。 下部结构具有芯片焊盘。 半导体器件还包括位于芯片焊盘上方的钝化层。 钝化层包括限定在其中的第一开口以暴露至少一部分芯片焊盘。 半导体器件还包括彼此间隔开并位于钝化层上方的至少两个相邻的再分配线。 所述至少两个再分配线分别通过相应的第一开口耦合到芯片焊盘。 半导体器件包括位于钝化层上方的第一绝缘层。 第一绝缘层包括在至少两个相邻再分布线之间延伸的空隙。

公开(公告)号：US20080076248A1

公开(公告)日：2008-03-27

申请号：US11589717

申请日：2006-10-31

Applicant: Soon-bum Kim ,  Sung-min Sim ,  Dong-hyeon Jang ,  Jae-sik Chung ,  Se-yong Oh

Inventor： Soon-bum Kim ,  Sung-min Sim ,  Dong-hyeon Jang ,  Jae-sik Chung ,  Se-yong Oh

IPC: H01L21/44

CPC classification number: H01L24/11 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/00014 ,  H01L2924/013 ,  H01L2924/01028

Abstract: Provided is a method of forming conductors (e.g., metal lines and/or bumps) for semiconductor devices and conductors formed from the same. First and second seed metal layers may be formed. At least one mask may be formed on a portion on which a conductor is to be formed. An exposed portion may be oxidized. The oxidized portion may be removed. A conductive structure may be formed on an upper surface of a portion which is not oxidized. The conductors may be metal lines and/or bumps. The conductive structures may be solder balls.

Abstract translation: 提供了形成半导体器件的导体（例如金属线和/或凸块）以及由其形成的导体的方法。 可以形成第一和第二种子金属层。 至少一个掩模可以形成在其上将形成导体的部分上。 暴露部分可能被氧化。 可以除去氧化部分。 可以在未被氧化的部分的上表面上形成导电结构。 导体可以是金属线和/或凸块。 导电结构可以是焊球。

公开(公告)号：US07312143B2

公开(公告)日：2007-12-25

申请号：US11717691

申请日：2007-03-14

Applicant: Myeong-Soon Park ,  Hyun-Soo Chung ,  In-Young Lee ,  Jae-Sik Chung ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Young-Hee Song ,  Seung-Kwan Ryu

Inventor： Myeong-Soon Park ,  Hyun-Soo Chung ,  In-Young Lee ,  Jae-Sik Chung ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Young-Hee Song ,  Seung-Kwan Ryu

IPC: H01L23/48

CPC classification number: H01L23/3114 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02165 ,  H01L2224/02335 ,  H01L2224/02351 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05557 ,  H01L2224/05569 ,  H01L2224/10125 ,  H01L2224/13006 ,  H01L2224/13011 ,  H01L2224/13018 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A wafer level chip scale package may have a gap provided between a solder bump and a bump land. The gap may be filled with a gas. A method of manufacturing a wafer level chip scale package may involve forming a redistribution line having a first opening, forming a seed metal layer having a second opening including an undercut portion, and forming the gap using the first and the second openings.

Abstract translation: 晶片级芯片级封装可以具有设置在焊料凸块和凸起焊盘之间的间隙。 间隙可以填充气体。 制造晶片级芯片级封装的方法可以包括形成具有第一开口的再分配线，形成具有包括底切部分的第二开口的种子金属层，以及使用第一和第二开口形成间隙。

公开(公告)号：US20060214293A1

公开(公告)日：2006-09-28

申请号：US11186763

申请日：2005-07-22

Applicant: Myeong-Soon Park ,  Hyun-Soo Chung ,  In-Young Lee ,  Jae-Sik Chung ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Young-Hee Song ,  Seung-Kwan Ryu

Inventor： Myeong-Soon Park ,  Hyun-Soo Chung ,  In-Young Lee ,  Jae-Sik Chung ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Young-Hee Song ,  Seung-Kwan Ryu

IPC: H01L21/44 ,  H01L23/48

CPC classification number: H01L23/3114 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02165 ,  H01L2224/02335 ,  H01L2224/02351 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05557 ,  H01L2224/05569 ,  H01L2224/10125 ,  H01L2224/13006 ,  H01L2224/13011 ,  H01L2224/13018 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A wafer level chip scale package may have a gap provided between a solder bump and a bump land. The gap may be filled with a gas. A method of manufacturing a wafer level chip scale package may involve forming a redistribution line having a first opening, forming a seed metal layer having a second opening including an undercut portion, and forming the gap using the first and the second openings.

Abstract translation: 晶片级芯片级封装可以具有设置在焊料凸块和凸起焊盘之间的间隙。 间隙可以填充气体。 制造晶片级芯片级封装的方法可以包括形成具有第一开口的再分配线，形成具有包括底切部分的第二开口的种子金属层，以及使用第一和第二开口形成间隙。

公开(公告)号：US20060073704A1

公开(公告)日：2006-04-06

申请号：US11210817

申请日：2005-08-25

Applicant: Se-young Jeong ,  In-young Lee ,  Sung-min Sim ,  Young-hee Song ,  Dong-hyeon Jang ,  Myeong-soon Park ,  Sun-young Park ,  Sun-bum Kim ,  Hyun-soo Chung

Inventor： Se-young Jeong ,  In-young Lee ,  Sung-min Sim ,  Young-hee Song ,  Dong-hyeon Jang ,  Myeong-soon Park ,  Sun-young Park ,  Sun-bum Kim ,  Hyun-soo Chung

IPC: H01L21/302 ,  H01L21/461 ,  B44C1/22

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/00014

Abstract: A method of forming a bump may involve providing a seed layer on a contact pad of a wafer. A shielding layer and a photosensitive mask layer may be formed on the seed layer. The photosensitive mask layer may be exposed and developed to form a mask pattern. An exposed portion of the shielding layer may be removed. The bump may be formed by plating the exposed seed layer.

Abstract translation: 形成凸块的方法可以包括在晶片的接触焊盘上提供种子层。 可以在种子层上形成屏蔽层和感光掩模层。 感光掩模层可以被曝光和显影以形成掩模图案。 可以去除屏蔽层的暴露部分。 可以通过电镀暴露的种子层来形成凸块。

公开(公告)号：US07855144B2

公开(公告)日：2010-12-21

申请号：US11589717

申请日：2006-10-31

Applicant: Soon-bum Kim ,  Sung-min Sim ,  Dong-hyeon Jang ,  Jae-sik Chung ,  Se-yong Oh

Inventor： Soon-bum Kim ,  Sung-min Sim ,  Dong-hyeon Jang ,  Jae-sik Chung ,  Se-yong Oh

IPC: H01L21/44

CPC classification number: H01L24/11 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/00014 ,  H01L2924/013 ,  H01L2924/01028

Abstract: Provided is a method of forming conductors (e.g., metal lines and/or bumps) for semiconductor devices and conductors formed from the same. First and second seed metal layers may be formed. At least one mask may be formed on a portion on which a conductor is to be formed. An exposed portion may be oxidized. The oxidized portion may be removed. A conductive structure may be formed on an upper surface of a portion which is not oxidized. The conductors may be metal lines and/or bumps. The conductive structures may be solder balls.

Abstract translation: 提供了形成半导体器件的导体（例如金属线和/或凸块）以及由其形成的导体的方法。 可以形成第一和第二种子金属层。 至少一个掩模可以形成在其上将形成导体的部分上。 暴露部分可能被氧化。 可以除去氧化部分。 可以在未被氧化的部分的上表面上形成导电结构。 导体可以是金属线和/或凸块。 导电结构可以是焊球。

公开(公告)号：US20090153171A1

公开(公告)日：2009-06-18

申请号：US12314360

申请日：2008-12-09

Applicant: Sang-Sik Lee ,  Yun-Ha Park ,  Sung-Min Sim ,  Myoung-Sub Kim

Inventor： Sang-Sik Lee ,  Yun-Ha Park ,  Sung-Min Sim ,  Myoung-Sub Kim

IPC: G01R31/28

CPC classification number: G01R31/2874

Abstract: An apparatus for testing objects includes a test board having electrical connection areas to connect to the objects, a chamber fixture located on the test board to form test chambers that are configured to individually receive the objects, a thermoelectric element provided to each test chamber to adjust the temperature of the object, and a temperature controller for individually controlling operations of the thermoelectric elements.

Abstract translation: 一种用于测试物体的装置包括具有连接到物体的电气连接区域的测试板，位于测试板上的腔室夹具，以形成被配置为分别接收物体的测试室，设置到每个测试室的热电元件以调整 物体的温度和用于单独控制热电元件的操作的温度控制器。

公开(公告)号：US07307342B2

公开(公告)日：2007-12-11

申请号：US11195361

申请日：2005-08-01

Applicant: Se-Young Jeong ,  Sung-Min Sim ,  Soon-Bum Kim ,  In-Young Lee ,  Young-Hee Song

Inventor： Se-Young Jeong ,  Sung-Min Sim ,  Soon-Bum Kim ,  In-Young Lee ,  Young-Hee Song

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/05 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05018 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: An interconnection structure includes an integrated circuit (IC) chip having internal circuitry and a terminal to electrically connect the internal circuitry to an external circuit, a passivation layer disposed on a top surface of the IC chip, the passivation layer configured to protect the internal circuitry and to expose the terminal, an input/output (I/O) pad, where the I/O pad includes a first portion in contact with the terminal and a second portion that extends over the passivation layer, and an electroless plating layer disposed on the I/O pad.

Abstract translation: 互连结构包括具有内部电路的集成电路（IC）芯片和用于将内部电路电连接到外部电路的端子，设置在IC芯片的顶表面上的钝化层，钝化层被配置为保护内部电路 以及使所述终端暴露于所述I / O焊盘包括与所述端子接触的第一部分和在所述钝化层上延伸的第二部分的输入/输出（I / O）焊盘，以及设置在所述钝化层上的无电镀层 I / O板。

公开(公告)号：US20070200216A1

公开(公告)日：2007-08-30

申请号：US11703900

申请日：2006-12-19

Applicant: Soon-Bum Kim ,  Ung-Kwang Kim ,  Kang-Wook Lee ,  Se-Young Jeong ,  Young-Hee Song ,  Sung-Min Sim

Inventor： Soon-Bum Kim ,  Ung-Kwang Kim ,  Kang-Wook Lee ,  Se-Young Jeong ,  Young-Hee Song ,  Sung-Min Sim

IPC: H01L23/02

CPC classification number: H01L21/563 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/274 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83194 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3511 ,  H01L2924/00

Abstract: Provided is a chip stack package that may include a lower semiconductor chip, an upper semiconductor chip stacked on the lower semiconductor chip, and at least one adhesive formed in space between the lower semiconductor chip and the upper semiconductor chip. The at least one adhesive may include a first adhesive and a second adhesive. The first adhesive may be formed in a portion of the space, and the second adhesive may be formed in the space except for a region in which the first adhesive is provided. The space between adjacent semiconductor chips may be completely filled with the at least one adhesive. Therefore, a chip stack package according to the exemplary embodiments of the present invention may exhibit improved mechanical stability and reliability.

Abstract translation: 提供了一种芯片堆叠封装，其可以包括下半导体芯片，堆叠在下半导体芯片上的上半导体芯片，以及形成在下半导体芯片和上半导体芯片之间的空间中的至少一个粘合剂。 所述至少一种粘合剂可以包括第一粘合剂和第二粘合剂。 第一粘合剂可以形成在空间的一部分中，并且第二粘合剂可以形成在除了设置第一粘合剂的区域之外的空间中。 相邻的半导体芯片之间的空间可以被至少一个粘合剂完全填充。 因此，根据本发明的示例性实施例的芯片堆叠封装可以表现出改进的机械稳定性和可靠性。

公开(公告)号：US20070176290A1

公开(公告)日：2007-08-02

申请号：US11717691

申请日：2007-03-14

Applicant: Myeong-Soon Park ,  Hyun-Soo Chung ,  In-Young Lee ,  Jae-Sik Chung ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Young-Hee Song ,  Seung-Kwan Ryu

Inventor： Myeong-Soon Park ,  Hyun-Soo Chung ,  In-Young Lee ,  Jae-Sik Chung ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Young-Hee Song ,  Seung-Kwan Ryu

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H01L23/3114 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02165 ,  H01L2224/02335 ,  H01L2224/02351 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05557 ,  H01L2224/05569 ,  H01L2224/10125 ,  H01L2224/13006 ,  H01L2224/13011 ,  H01L2224/13018 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A wafer level chip scale package may have a gap provided between a solder bump and a bump land. The gap may be filled with a gas. A method of manufacturing a wafer level chip scale package may involve forming a redistribution line having a first opening, forming a seed metal layer having a second opening including an undercut portion, and forming the gap using the first and the second openings.