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    Method for implementing poly pre-doping in deep sub-micron process
    11.
    发明申请
    Method for implementing poly pre-doping in deep sub-micron process 审中-公开
    在深亚微米工艺中实施多种预掺杂的方法

    公开(公告)号：US20050118802A1

    公开(公告)日：2005-06-02

    申请号：US10991839

    申请日：2004-11-18

    Applicant: Chang-Sheng Tsao ,  Yi-Hang Chen ,  Jung-Hui Kao ,  Yen-Ming Chen ,  Pu-Fang Chen ,  Lin-June Wu

    Inventor： Chang-Sheng Tsao ,  Yi-Hang Chen ,  Jung-Hui Kao ,  Yen-Ming Chen ,  Pu-Fang Chen ,  Lin-June Wu

    IPC: H01L21/265 ,  H01L21/28 ,  H01L21/324 ,  H01L21/331 ,  H01L29/78

    CPC classification number: H01L21/28035 ,  H01L21/265 ,  H01L21/324 ,  H01L29/78

    Abstract: Method for reducing dopant contamination during the fabrication of semiconductor devices is provided. The method includes doping a first layer, such as a polysilicon layer. During a subsequent annealing process, a gas, such as nitrogen, oxygen, a combination thereof, or the like, is introduced. The gas causes a cap layer to be formed over the first layer, preventing or reducing out-diffusing of the dopants and contamination of the process chamber. In a preferred embodiment, the gas is introduced during the ramp-up stage of the annealing process. The cap layer may be removed prior to etching the first layer.

    Abstract translation: 提供了在制造半导体器件期间减少掺杂剂污染的方法。 该方法包括掺杂第一层，例如多晶硅层。 在随后的退火过程中，引入气体，例如氮气，氧气，其组合等。 气体导致在第一层上形成覆盖层，防止或减少掺杂物的扩散和处理室的污染。 在优选实施例中，在退火过程的加速阶段期间引入气体。 在蚀刻第一层之前可以去除覆盖层。

    Optical sensor by using tunneling diode
    12.
    发明授权
    Optical sensor by using tunneling diode 有权
    光传感器采用隧道二极管

    公开(公告)号：US06693317B2

    公开(公告)日：2004-02-17

    申请号：US10437147

    申请日：2003-05-13

    Applicant: Ho-Yin Yiu ,  Chein-Ling Jan ,  Jen-Pan Wang ,  Lin-June Wu

    Inventor： Ho-Yin Yiu ,  Chein-Ling Jan ,  Jen-Pan Wang ,  Lin-June Wu

    IPC: H01L2976

    CPC classification number: H01L31/101 ,  H01L31/18

    Abstract: A method of fabricating a tunneling photodiode is presented comprised of the following steps: forming a p-well in an n-type substrate, forming a thin insulating layer over the surface of the p-type material, and then forming a thin n-type layer over the insulating layer. Preferably, the n and p type semiconductor material could be silicon and the insulating layer could be between about 30 to 40 angstroms of gate quality silicon dioxide. In other embodiments of the invention the materials of either electrode are either n or p-type semiconductors or metals.

    Abstract translation: 提出一种制造隧道光电二极管的方法，包括以下步骤：在n型衬底中形成p阱，在p型材料的表面上形成薄的绝缘层，然后形成薄的n型 层在绝缘层上。 优选地，n型和p型半导体材料可以是硅，并且绝缘层可以在约30至40埃的栅极质量的二氧化硅之间。 在本发明的其它实施方案中，任一电极的材料是n型或p型半导体或金属。

    Use of a capping layer to reduce particle evolution during sputter pre-clean procedures
    14.
    发明授权
    Use of a capping layer to reduce particle evolution during sputter pre-clean procedures 有权
    在溅射预清洁过程中使用覆盖层来减少颗粒的发生

    公开(公告)号：US06531382B1

    公开(公告)日：2003-03-11

    申请号：US10140662

    申请日：2002-05-08

    Applicant: Tao Cheng ,  Wen-Hsin Huang ,  Jiun-Pyng You ,  Lin-June Wu ,  Shih-Tzung Chang ,  Ming-Jei Lee ,  Chun-Chang Chen ,  Yu-Ku Lin ,  Tong-Hua Kuan ,  Ying-Lang Wang

    Inventor： Tao Cheng ,  Wen-Hsin Huang ,  Jiun-Pyng You ,  Lin-June Wu ,  Shih-Tzung Chang ,  Ming-Jei Lee ,  Chun-Chang Chen ,  Yu-Ku Lin ,  Tong-Hua Kuan ,  Ying-Lang Wang

    IPC: H01L213205

    CPC classification number: H01L21/76802 ,  H01L21/76838

    Abstract: A process for preparing a surface of a lower level metal structure, exposed at the bottom of a sub-micron diameter opening, to allow a low resistance interface to be obtained when overlaid with an upper level metal structure, has been developed. A disposable, capping insulator layer is first deposited on the composite insulator layer in which the sub-micron diameter opening will be defined in, to protect underlying components of the composite insulator from a subsequent metal pre-metal procedure. After anisotropically defining the sub-micron diameter opening in the capping insulator, and composite insulator layers, and after removal of the defining photoresist shape, an argon sputtering procedure is used to remove native oxide from the surface of the lower level metal structure. In addition to native oxide removal the argon sputtering procedure, featuring a negative DC bias applied to the substrate, also removes the capping insulator layer from the top surface of the composite insulator layer. An in situ metal deposition then allows a clean interface to result between the overlying metal layer, and the underlying plasma treated, metal surface.

    Abstract translation: 已经开发了制备在亚微米直径开口的底部露出的下层金属结构的表面以允许在与上层金属结构重叠时获得低电阻界面的方法。 首先将一次性封盖绝缘体层沉积在复合绝缘体层上，在该复合绝缘层上将限定亚微米直径的开口，以保护复合绝缘子的下面的部件免于后续的金属预金属工艺。 在各向异性地限定封盖绝缘体中的亚微米直径开口和复合绝缘体层之后，并且在去除限定的光致抗蚀剂形状之后，使用氩溅射方法从下层金属结构的表面去除自然氧化物。 除了自然氧化物除去之外，具有施加到衬底的负DC偏压的氩溅射工艺也从复合绝缘体层的顶表面去除封盖绝缘体层。 原位金属沉积然后允许在上覆的金属层和下面的等离子体处理的金属表面之间产生干净的界面。

    ESD implantation scheme for 0.35 .mu.m 3.3V 70A gate oxide process
    15.
    发明授权
    ESD implantation scheme for 0.35 .mu.m 3.3V 70A gate oxide process 失效
    用于0.35μm3.3V 70A栅极氧化工艺的ESD注入方案

    公开(公告)号：US5953601A

    公开(公告)日：1999-09-14

    申请号：US24480

    申请日：1998-02-17

    Applicant: Ruey-Yun Shiue ,  Chin-Shan Hou ,  Yi-Hsun Wu ,  Lin-June Wu

    Inventor： Ruey-Yun Shiue ,  Chin-Shan Hou ,  Yi-Hsun Wu ,  Lin-June Wu

    IPC: H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H01L21/8236

    CPC classification number: H01L27/0266 ,  H01L21/823814 ,  H01L27/0922

    Abstract: A method is disclosed for improving the ESD protection of gate oxide in ultra large scale integrated circuits of 0.35 .mu.m technology or less, approaching 0.25 .mu.m. This is accomplished by providing a silicon substrate and forming thereon product FET device circuits and ESD protection device circuits. In forming the ESD source/drain regions, the implantation species is changed from phosphorous to boron, thereby reducing junction breakdown voltage. Ion implantation is performed judiciously in areas with high leakage and capacitance. Hence improvement is accomplished though reduced breakdown voltage, as well as through reduced leakage and capacitance of the junction. Furthermore, ion implantation is performed using a photoresist mask prior to the formation of silicidation over the contact area. This avoids the problem of silicide degradation and the concomitant increase in contact resistance through the transportation of metal ions into depletion region of junction during high energy ESD implantation.

    Abstract translation: 公开了一种提高0.35μm技术以下，接近0.25μm的超大规模集成电路中的栅极氧化物的ESD保护的方法。 这通过提供硅衬底并在其上形成产品FET器件电路和ESD保护器件电路来实现。 在形成ESD源极/漏极区域时，注入物质从磷变为硼，从而降低结击穿电压。 离子注入在具有高泄漏和电容的区域中明智地执行。 因此，通过降低击穿电压以及通过减小接合部的泄漏和电容来实现改进。 此外，在接触区域上形成硅化物之前，使用光致抗蚀剂掩模进行离子注入。 这避免了硅化物降解的问题，并且通过在高能量ESD注入期间通过将金属离子输送到结的耗尽区域而引起的接触电阻的伴随增加。

    Method of protecting an alignment mark in a semiconductor manufacturing process with CMP
    16.
    发明授权
    Method of protecting an alignment mark in a semiconductor manufacturing process with CMP 失效
    通过CMP在半导体制造工艺中保护对准标记的方法

    公开(公告)号：US5801090A

    公开(公告)日：1998-09-01

    申请号：US845608

    申请日：1997-04-25

    Applicant: Lin-June Wu ,  Jau-Jey Wang

    Inventor： Lin-June Wu ,  Jau-Jey Wang

    IPC: H01L21/3105 ,  H01L23/544 ,  H01L21/28

    CPC classification number: H01L23/544 ,  H01L21/31053 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975

    Abstract: The present invention is a method of protecting an alignment mark in semiconductor manufacturing process with CMP. This invention utilizes a via mask or masking blade to remove the intermetal dielectric layer on a wide clear -out window using two etching steps. One etching step is performed before intermetal dielectric layer polish. The other etching step is performed after intermetal dielectric layer polish. Thus, there is no intermetal dielectric layer remained on the alignment mark and the alignment mark keeps the original shape.

    Abstract translation: 本发明是利用CMP在半导体制造工艺中保护对准标记的方法。 本发明利用通孔掩模或掩模刀片，使用两个蚀刻步骤在宽的透明窗口上去除金属间电介质层。 在金属间电介质层抛光之前进行一个蚀刻步骤。 在金属间电介质层抛光之后进行另一蚀刻步骤。 因此，在对准标记上不存在金属间电介质层，并且对准标记保持原来的形状。

    Tunable threshold voltage of a thick field oxide ESD protection device with a N-field implant
    19.
    发明授权
    Tunable threshold voltage of a thick field oxide ESD protection device with a N-field implant 有权
    具有N场注入的厚场氧化物ESD保护器件的可调阈值电压

    公开(公告)号：US06717220B2

    公开(公告)日：2004-04-06

    申请号：US10236534

    申请日：2002-09-06

    Applicant: Tao Cheng ,  Jyh-Cheng You ,  Lin-June Wu

    Inventor： Tao Cheng ,  Jyh-Cheng You ,  Lin-June Wu

    IPC: H01L2362

    CPC classification number: H01L29/66613 ,  H01L27/0266

    Abstract: A structure and a process for manufacturing semiconductor devices with improved ESD protection for high voltage applications is described. A thick field gate oxide N channel field effect transistor (FET) device with a tunable threshold voltage (Vt) is developed at the input/output to the internal active circuits for the purpose of providing ESD protection for applications in the 9 volt and higher range. The FET threshold voltage determines the ESD protection characteristics. A N-field implant is used to provide a dopant region under the thick oxide gate element which has the effect of modifying the threshold voltage (Vt) of this device enabling the device turn-on to be “tuned” to more closely match the application requirements of the internal semiconductor circuits. The gate electrical contact is completed by using either a metal gate electrode or polysilicon gate element. The gate and drain of the thick oxide FET device are connected to the input/output connection pad of the internal semiconductor circuits which also enhances ESD protection. The FET source element is connected to another voltage source, typically ground, providing a path to shunt the current from an ESD incident thereby protecting the internal circuitry from damage.

    Abstract translation: 描述了用于制造具有改进的用于高电压应用的ESD保护的半导体器件的结构和工艺。 在内部有源电路的输入/输出处开发出具有可调阈值电压（Vt）的厚栅极氧化物N沟道场效应晶体管（FET）器件，用于为9伏及更高范围内的应用提供ESD保护 。 FET阈值电压决定ESD保护特性。 使用N场注入来提供厚氧化物栅极元件下方的掺杂剂区域，该掺杂剂区域具有改变该器件的阈值电压（Vt）的效果，使得器件导通被“调谐”以更紧密地匹配应用 内部半导体电路的要求。 通过使用金属栅极电极或多晶硅栅极元件来完成栅极电接触。 厚氧化物FET器件的栅极和漏极连接到内部半导体电路的输入/输出连接焊盘，这也增强了ESD保护。 FET源极元件连接到通常为接地的另一个电压源，提供了从ESD入射分流电流的路径，从而保护内部电路免受损坏。

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