公开(公告)号：US5014241A

公开(公告)日：1991-05-07

申请号：US337219

申请日：1989-04-12

Applicant: Mikio Asakura ,  Kazuyasu Fujishima ,  Yoshio Matsuda

Inventor： Mikio Asakura ,  Kazuyasu Fujishima ,  Yoshio Matsuda

IPC: G11C11/401 ,  G11C5/02 ,  G11C5/06 ,  G11C7/14 ,  G11C7/18 ,  G11C11/4096 ,  G11C11/4097 ,  G11C11/4099 ,  H01L21/8242 ,  H01L27/108

CPC classification number: G11C5/025 ,  G11C11/4096 ,  G11C11/4097 ,  G11C11/4099 ,  G11C5/063 ,  G11C7/14 ,  G11C7/18

Abstract: Each of sense amplifiers is coupled to two bit lines with another bit line being interposed therebetween. Information stored in a memory cell is read out onto one of the two bit lines coupled to each of the sense ampliers, while a reference potential is read out onto the other bit line. Outside of the two bit lines, a reference potential is respectively read out onto other bit lines adjacent to the two bit lines. The information stored in the memory cell is read out onto the other bit line between the two bit lines.

Abstract translation: 读出放大器中的每一个耦合到两个位线，另一个位线插在它们之间。 存储在存储器单元中的信息被读出到耦合到每个读出放大器的两个位线中的一个，同时将参考电位读出到另一个位线上。 在两个位线之外，将参考电位分别读出到与两个位线相邻的其它位线上。 存储在存储单元中的信息被读出到两个位线之间的另一位线上。

公开(公告)号：US4977542A

公开(公告)日：1990-12-11

申请号：US400898

申请日：1989-08-30

Applicant: Yoshio Matsuda ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Masaki Tsukude

Inventor： Yoshio Matsuda ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Masaki Tsukude

IPC: G11C11/401 ,  G11C7/14 ,  G11C7/18 ,  G11C8/14

CPC classification number: G11C7/14 ,  G11C7/18 ,  G11C8/14

Abstract: An arrangement for providing a compensation of capacitance coupling between word lines and bit lines in a memory structure including twisted bit lines. Two dummy word lines maintained at a predetermined potential are formed at a twisted portion of a pair of bit lines. Dummy cells are provided at respective twisted portions of the dummy word lines and the bit lines. A plurality of word lines are formed in a direction intersecting with the bit lines and the word lines are divided into four word line groups according to positions of the twisted portions of the bit line pairs. When an arbitrary word line is selected, a potential of at least one dummy word line corresponding to the word line group to which the selected word line belongs is lowered. Consequently, the rise of the potential of the bit lines caused by the selection of the word line is compensated for by the lowering of the potential of at least one dummy word line, making it possible to decrease errors in reading. Particular cell layer arrangements simplify increase in integration density in the combination of dummy cell compensation with the twisted bit line balancing of capacitance coupling.

Abstract translation: 一种用于在包括扭转位线的存储器结构中提供字线和位线之间的电容耦合补偿的装置。 保持在预定电位的两个虚拟字线形成在一对位线的扭转部分。 在虚拟字线和位线的相应扭转部分设置虚拟单元。 在与位线相交的方向上形成多个字线，并且根据位线对的扭绞部分的位置将字线分成四个字线组。 当选择任意字线时，与所选字线所属的字线组对应的至少一个虚拟字线的电位降低。 因此，通过降低至少一个虚拟字线的电位来补偿由字线的选择引起的位线的电位的上升，使得可以减少读取中的误差。 特殊的单元层布置简化了虚拟单元补偿与电容耦合的扭转位线平衡组合的集成密度的增加。

公开(公告)号：US4855953A

公开(公告)日：1989-08-08

申请号：US158323

申请日：1988-02-19

Applicant: Katsuhiro Tsukamoto ,  Masahiro Shimizu ,  Kazuyasu Fujishima ,  Yoshio Matsuda

Inventor： Katsuhiro Tsukamoto ,  Masahiro Shimizu ,  Kazuyasu Fujishima ,  Yoshio Matsuda

IPC: G11C11/404 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/417

CPC classification number: H01L27/10861 ,  G11C11/404 ,  H01L27/10829 ,  H01L29/41725 ,  H01L29/41766 ,  H01L29/66181

Abstract: A dynamic RAM comprises an array of memory cells, each of the memory cells comprising a single access transistor and a charge storage region. The charge storage region comprises a first capacitor memory including a P.sup.+ region serving as an opposite electrode formed in the inner surface of a trench formed in a P type silicon substrate, a first capacitor dielectric film formed on the P.sup.+ region and a common electrode layer serving as a memory terminal formed on the first capacitor dielectric film, and a second memory capacitor including the common electrode layer, a second capacitor dielectric film formed on the common electrode layer and a cell plate electrode formed on the second capacitor dielectric film. The memory terminal and a drain region of the access transistor are connected in a self-aligning manner by an electrode having a sidewall shape which is in contact with an end of the memory terminal. Thus, a contact hole need not be formed in the first capacitor dielectric film, so that decrease of the electrical reliability of the first capacitor dielectric film can be prevented. The drain region of the access transistor may be formed by self-alignment with the contact portion of the common electrode layer.

Abstract translation: 动态RAM包括存储器单元的阵列，每个存储器单元包括单个存取晶体管和电荷存储区域。 电荷存储区域包括第一电容器存储器，其包括形成在形成于P型硅衬底中的沟槽的内表面中的用作相对电极的P +区，形成在P +区上的第一电容器电介质膜和用于 作为形成在第一电容器电介质膜上的存储器端子，以及包括公共电极层的第二存储电容器，形成在公共电极层上的第二电容器电介质膜和形成在第二电容器电介质膜上的单元板电极。 存取晶体管的存储器端子和漏极区域通过具有与存储器端子的端部接触的侧壁形状的电极以自对准的方式连接。 因此，不需要在第一电容器电介质膜中形成接触孔，从而可以防止第一电容器电介质膜的电可靠性的降低。 存取晶体管的漏极区可以通过与公共电极层的接触部分进行自对准而形成。

公开(公告)号：US4719597A

公开(公告)日：1988-01-12

申请号：US766279

申请日：1985-08-16

Applicant: Masaki Kumanoya ,  Kazuyasu Fujishima ,  Hideshi Miyatake ,  Hideto Hidaka ,  Katsumi Dosaka

Inventor： Masaki Kumanoya ,  Kazuyasu Fujishima ,  Hideshi Miyatake ,  Hideto Hidaka ,  Katsumi Dosaka

IPC: G11C11/407 ,  G11C7/06 ,  G11C7/22 ,  G11C11/401 ,  G11C11/409 ,  G11C7/00 ,  G11C7/02 ,  G11C8/00

CPC classification number: G11C7/22 ,  G11C7/06

Abstract: A cut-off clock .phi..sub.5 generated by a cut-off clock generation circuit PG is supplied to a decode circuit DEC. The decode circuit DEC decodes the cut-off clock .phi..sub.5 to produce two types of cut-off clocks .phi..sub.5L and .phi..sub.5R. The two types of cut-off clocks .phi..sub.5L and .phi..sub.5R are supplied to a control clock generation circuit as shown in FIG. 3 or 11, which in turn produces control clocks .phi..sub.2L and .phi..sub.2R. The control clocks .phi..sub.2L and .phi..sub.2R are supplied to a shared sense amplifier of FIG. 1, to control on-off operations of transfer transistors 7.sub.L, 8.sub.L, 7.sub.R and 8.sub.R.

Abstract translation: 由截止时钟产生电路PG产生的截止时钟phi 5被提供给解码电路DEC。 解码电路DEC解码截止时钟phi 5以产生两种类型的截止时钟phi 5L和phi 5R。 两种类型的截止时钟phi 5L和phi 5R被提供给如图5所示的控制时​​钟产生电路。 3或11，其又产生控制时钟phi 2L和phi 2R。 控制时钟phi 2L和phi 2R被提供给图1的共享读出放大器。 以控制传输晶体管7L，8L，7R和8R的导通截止操作。

公开(公告)号：US4672582A

公开(公告)日：1987-06-09

申请号：US738262

申请日：1985-05-28

Applicant: Yasumasa Nishimura ,  Kazuyasu Fujishima ,  Masaki Kumanoya

Inventor： Yasumasa Nishimura ,  Kazuyasu Fujishima ,  Masaki Kumanoya

IPC: H01L21/66 ,  G11C29/00 ,  G11C29/34 ,  H01L21/822 ,  H01L27/04 ,  G11C7/00

CPC classification number: G11C29/34

Abstract: A semiconductor device is provided which can be efficiently subjected to a function test at a high speed by write/read operations for each plurality of bits. The semiconductor device according to the present invention comprises an encoder for encoding a 1-bit signal to a signal of a plurality of bits and a decoder receiving a signal of a plurality of bits for decoding the same to a 1-bit signal in response to the states thereof, so as to simultaneously write each bit of the plurality of bits from the encoder in each corresponding memory cell of a plurality of simultaneously selected memory cells in a writing test mode, and to simultaneously read information signals stored in the plurality of simultaneously selected memory cells in a reading test mode thereby to decode the signals to a 1-bit signal corresponding to the plurality of information signals.

Abstract translation: 提供一种半导体器件，其能够通过每个位的写入/读取操作而被高效率地进行功能测试。 根据本发明的半导体器件包括：编码器，用于将1比特信号编码为多个比特的信号;以及解码器，其接收多个比特的信号，以将其解码为1比特信号，以响应于 其状态，以便以写入测试模式在多个同时选择的存储单元的每个对应的存储单元中同时从编码器写入多个位的每一位，并同时读取同时存储在多个存储单元中的信息信号 在读取测试模式中选择的存储单元，从而将信号解码为对应于多个信息信号的1位信号。

公开(公告)号：US06859403B2

公开(公告)日：2005-02-22

申请号：US10815798

申请日：2004-04-02

Applicant: Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

Inventor： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

IPC: G11C11/407 ,  G11C5/14 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08 ,  G11C11/401 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4091 ,  H01L21/8242 ,  H01L27/108

CPC classification number: G11C11/4085 ,  G11C5/14 ,  G11C5/147 ,  G11C7/062 ,  G11C7/067 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/4091

Abstract: Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss′, and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss′.

Abstract translation: 第一和第二晶体管的漏极连接到诸如与确定存储器单元中的电位相关的读出放大器的内部电路的低电平线。 第一个晶体管的栅极二极管连接到感测驱动线，其源极接地。 第二晶体管在其栅极处接收内部产生的信号，其源极接地。 在待机状态下，将感测驱动线的电位设定为比第一晶体管的阈值电压Vthn高于所述字线的低电平，并将其用作虚设GND电位Vss'，而在激活状态下，第二晶体管为 导通，以防止感测驱动线从虚拟GND电位Vss'浮起。

公开(公告)号：US06272055B1

公开(公告)日：2001-08-07

申请号：US09168962

申请日：1998-10-09

Applicant: Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

Inventor： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

IPC: G11C700

CPC classification number: G11C11/4085 ,  G11C5/14 ,  G11C5/147 ,  G11C7/062 ,  G11C7/067 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/4091

Abstract: Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss′, and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss′.

公开(公告)号：US06214664B1

公开(公告)日：2001-04-10

申请号：US09443016

申请日：1999-11-18

Applicant: Hiroshi Kimura ,  Tadashi Nishimura ,  Takahiro Tsuruda ,  Kazutami Arimoto ,  Tadato Yamagata ,  Kazuyasu Fujishima

Inventor： Hiroshi Kimura ,  Tadashi Nishimura ,  Takahiro Tsuruda ,  Kazutami Arimoto ,  Tadato Yamagata ,  Kazuyasu Fujishima

IPC: H01L218242

CPC classification number: H01L27/10852

Abstract: In a semiconductor device and a method of manufacturing the same, an isolating and insulating film is provided at an end neighboring to a second impurity region with a groove extended to a semiconductor substrate. This removes a crystal defect existed at the end of the isolating and insulating film, and thus prevents leak of a current at this portion from a storage node. Consequently, provision of the groove at the edge portion of the isolating oxide film neighboring to the impurity region removes a crystal defect at this region, and thus eliminates a possibility of leak of a current.

Abstract translation: 在半导体器件及其制造方法中，隔离绝缘膜设置在与第二杂质区相邻的端部处，并且沟槽延伸到半导体衬底。 这消除了隔离和绝缘膜末端存在的晶体缺陷，从而防止在该部分处的电流从存储节点泄漏。 因此，在与杂质区相邻的隔离氧化膜的边缘部分处设置沟槽消除了该区域的晶体缺陷，从而消除了电流泄漏的可能性。

公开(公告)号：US5943273A

公开(公告)日：1999-08-24

申请号：US899143

申请日：1997-07-23

Applicant: Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

Inventor： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

IPC: G11C11/407 ,  G11C5/14 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08 ,  G11C11/401 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4091 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

CPC classification number: G11C11/4085 ,  G11C11/4074 ,  G11C11/4091 ,  G11C5/14 ,  G11C5/147 ,  G11C7/062 ,  G11C7/067 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08

Abstract: Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss', and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss'.

公开(公告)号：US5687123A

公开(公告)日：1997-11-11

申请号：US312968

申请日：1994-09-30

Applicant: Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

Inventor： Hideto Hidaka ,  Mikio Asakura ,  Kazuyasu Fujishima ,  Tsukasa Ooishi ,  Kazutami Arimoto ,  Shigeki Tomishima ,  Masaki Tsukude

IPC: G11C11/407 ,  G11C5/14 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08 ,  G11C11/401 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4091 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

CPC classification number: G11C11/4085 ,  G11C11/4074 ,  G11C11/4091 ,  G11C5/14 ,  G11C5/147 ,  G11C7/062 ,  G11C7/067 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08

Abstract: Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss', and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss'.

Abstract translation: 第一和第二晶体管的漏极连接到诸如与确定存储器单元中的电位相关的读出放大器的内部电路的低电平线。 第一个晶体管的栅极二极管连接到感测驱动线，其源极接地。 第二晶体管在其栅极处接收内部产生的信号，其源极接地。 在待机状态下，将感测驱动线的电位设定为比第一晶体管的阈值电压Vthn高于所述字线的低电平，并将其用作虚设GND电位Vss'，而在激活状态下，第二晶体管为 导通，以防止感测驱动线从虚拟GND电位Vss'浮起。