公开(公告)号：US20210204401A1

公开(公告)日：2021-07-01

申请号：US16914861

申请日：2020-06-29

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Yu-Chen Ma ,  Hsin-Hao Huang ,  Wen-Fu Chou ,  Gwo-Shyan Sheu

IPC: H05K1/02

Abstract: A flexible circuit board includes a flexible substrate and a stiffening structure, a stiffening area is defined on a bottom surface of the flexible substrate, and the stiffening structure includes a first stiffener and a second stiffener. The first stiffener is disposed on the stiffening area of the bottom surface and the second stiffener is disposed on the first stiffener such that the first stiffener is located between the flexible substrate and the second stiffener. The flexible substrate is protected from punch damage caused by stress concentrations because a cutting line of the flexible substrate only passes through the first stiffener.

公开(公告)号：US20210159159A1

公开(公告)日：2021-05-27

申请号：US16833826

申请日：2020-03-30

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chun-Te Lee ,  Chih-Ming Peng ,  Hui-Yu Huang ,  Yin-Chen Lin

IPC: H01L23/498 ,  H01L23/00

Abstract: A layout structure of double-sided flexible circuit board includes a flexible substrate having a first surface and a second surface, a first circuit layer and a second circuit layer. An inner bonding region is defined on the first surface and an inner supporting region is defined on the second surface according to the inner bonding region. The first circuit layer is located on the first surface and includes first conductive lines which each includes an inner lead located on the inner bonding region. The second circuit layer is located on the second surface and includes second conductive lines which each includes an inner supporting segment located on the inner supporting region. A width difference between any two of the inner supporting segment of the second conductive lines is less than 8 μm.

公开(公告)号：US10808331B2

公开(公告)日：2020-10-20

申请号：US15867878

申请日：2018-01-11

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Cheng-Hung Shih ,  Tsuo-Yun Chu ,  Xin-Wei Lo ,  Nian-Cih Yang

IPC: C25D21/04 ,  C25D17/00 ,  C25D21/10 ,  C25D17/06 ,  C25D5/08

Abstract: An electroplating system for depositing a plating material on an object includes a pressure device and an anode element. The pressure device includes a lid having first and second through holes and a base having a chamber, conduction holes and third through holes located in the chamber. Each of the conduction tubes includes a conduction hole connecting to one of the third through holes. The lid covers the chamber, the first through holes communicate with the chamber for spraying an electroplating solution toward the object and the second through holes reveal the conduction holes. A passage of electric force line is formed in the connected holes and the third through holes filled with the electroplating solution, and the anode element is located outside the passage of electric force line. The electroplating system can prevent defective plating and enhance plating efficiency.

公开(公告)号：US20190252207A1

公开(公告)日：2019-08-15

申请号：US15960707

申请日：2018-04-24

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chin-Tang Hsieh

IPC: H01L21/48 ,  H01L23/498 ,  H01L21/66

CPC classification number: H01L21/481 ,  H01L22/20 ,  H01L23/145 ,  H01L23/49838 ,  H01L23/4985

Abstract: A semiconductor substrate includes a carrier and leads formed on the carrier, and a space exists between the adjacent leads and reveals a surface of the carrier. A processing method of the semiconductor substrate uses a laser beam passing through the space to etch the carrier such that there are ditches recessed on the carrier. The ditches can increase fluidity of coating fluid, such as underfill, ACF and solder resist. Furthermore, during etching the carrier, the laser beam also can remove residues remained between the leads to improve yield of the semiconductor substrate.

公开(公告)号：US10168582B1

公开(公告)日：2019-01-01

申请号：US15841424

申请日：2017-12-14

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chun-Yang Su ,  Jhao-Shin Wang ,  Nian-Cih Yang ,  Xin-Wei Lo

IPC: H01L23/495 ,  G02F1/1339 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498

Abstract: A chip package includes a flexible substrate, a chip, a pressure-proof member and a reinforcement sheet. The chip and the pressure-proof member are located on a first surface of the flexible substrate, and the reinforcement sheet is located on a second surface of the flexible substrate. The pressure-proof member at least includes a pair of pressure-proof ribs which are located outside of the chip oppositely. The pressure-proof ribs located outside the chip can protect the chip from the damage caused by the pressure of other component (e.g. curved panel) except the chip package.

公开(公告)号：US09653376B1

公开(公告)日：2017-05-16

申请号：US15162758

申请日：2016-05-24

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chin-Tang Hsieh

IPC: H01L23/10 ,  H01L23/34 ,  H01L23/367 ,  H01L23/373 ,  H01L23/00

CPC classification number: H01L23/3675 ,  H01L23/3736 ,  H01L23/562 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16238 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/16251 ,  H01L2924/3511

Abstract: A heat dissipation package structure includes a substrate, a chip disposed on the substrate and a heat dissipation sheet. The heat dissipation sheet comprises a covering portion disposed on a back surface of the chip, a first lateral covering portion disposed on a first lateral surface of the chip and a first conducting portion disposed on the substrate. The back surface comprises a first width, the covering portion comprises a second width, the chip comprises a thickness, and there is an interval between the chip and the substrate. The second width is not larger than summation of the first width, double the interval and double the thickness for making the chip disposed between the heat dissipation sheet and the substrate is not within a completely sealed space so as to prevent the heat dissipation sheet from deformation and separation from the chip or the substrate cause of air expansion.

公开(公告)号：US08823169B2

公开(公告)日：2014-09-02

申请号：US13644749

申请日：2012-10-04

Applicant: Chipbond Technology Corporation

Inventor： Chih-Ming Kuo ,  Lung-Hua Ho ,  Shih-Chieh Chang ,  Chia-Yeh Huang ,  Chin-Tang Hsieh

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L21/76885 ,  H01L21/4853 ,  H01L23/48 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11903 ,  H01L2224/13006 ,  H01L2224/13016 ,  H01L2224/13023 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A semiconductor manufacturing method includes providing a carrier; forming a first photoresist layer; forming plural core portions; removing the first photoresist layer; forming a second photoresist layer; forming a plurality of connection portions, each of the plurality of connection portions includes a first connection layer and a second connection layer and connects to each of the core portions to form a hybrid bump, wherein each of the first connection layers comprises a base portion, a projecting portion and an accommodating space, each base portion comprises an upper surface, each projecting portion is protruded to the upper surface and located on top of each core portion, each accommodating space is located outside each projecting portion, the second connection layers cover the projecting portions and the upper surfaces, and the accommodating spaces are filled by the second connection layers; removing the second photoresist layer to reveal the hybrid bumps.

Abstract translation: 半导体制造方法包括提供载体; 形成第一光致抗蚀剂层; 形成多个芯部; 去除第一光致抗蚀剂层; 形成第二光致抗蚀剂层; 形成多个连接部分，所述多个连接部分中的每一个包括第一连接层和第二连接层，并且连接到每个所述芯部分以形成混合凸块，其中每个所述第一连接层包括基部， 突出部分和容纳空间，每个基部包括上表面，每个突出部分突出到上表面并且位于每个芯部的顶部，每个容纳空间位于每个突出部分的外侧，第二连接层覆盖 突出部分和上表面，并且容纳空间被第二连接层填充; 去除第二光致抗蚀剂层以露出混合凸块。

公开(公告)号：US20140217578A1

公开(公告)日：2014-08-07

申请号：US13833347

申请日：2013-03-15

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Lung-Hua Ho ,  Fei-Jain Wu ,  Chih-Ming Kuo ,  Shih-Chieh Chang ,  Chia-Jung Tu

IPC: H01L23/00

CPC classification number: H01L24/81 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/13006 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13562 ,  H01L2224/1601 ,  H01L2224/16503 ,  H01L2224/81048 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81898 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/00012

Abstract: A semiconductor package process includes the following steps, providing a first substrate having a first metal bump, the first metal bump comprises a joint portion having a first softening point; providing a second substrate having a second metal bump having a top surface, a lateral surface and a second softening point, wherein the first softening point is smaller than the second softening point; performing a heating procedure to make the joint portion of the first metal bump become a softened state; and laminating the first substrate on the second substrate to make the second metal bump embedded into the joint portion in the softened state to make the top surface and the lateral surface of the at least one second metal bump being clad extendedly by compressing the joint portion in the softened state.

Abstract translation: 半导体封装工艺包括以下步骤：提供具有第一金属凸块的第一衬底，第一金属凸块包括具有第一软化点的接合部分; 提供具有第二金属凸块的第二基板，其具有顶表面，侧表面和第二软化点，其中所述第一软化点小于所述第二软化点; 执行加热程序以使第一金属凸块的接合部分变为软化状态; 并且将所述第一基板层压在所述第二基板上，以使所述第二金属凸块以软化状态嵌入所述接合部，以使所述至少一个第二金属凸块的顶表面和所述侧表面通过压缩所述接合部分 软化状态。

公开(公告)号：US08796824B1

公开(公告)日：2014-08-05

申请号：US14014568

申请日：2013-08-30

Applicant: Chipbond Technology Corporation

Inventor： Chin-Tang Hsieh ,  Shyh-Jen Guo ,  You-Ming Hsu

IPC: H01L23/58 ,  H01L29/06 ,  H01L23/00 ,  H01L23/28 ,  H01L23/532

CPC classification number: H01L23/562 ,  H01L23/28 ,  H01L23/3192 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure having a first corner includes a carrier, a first protective layer, a second protective layer, and a third protective layer. The carrier comprises a carrier surface having a protection-layered disposing zone. The first protective layer comprises a first surface having a first disposing zone, a first anti-stress zone and a first exposing zone, the first anti-stress zone is located at a corner of the first disposing zone, the second protective layer is disposed at the first disposing zone. The second protective layer comprises a second surface having a second disposing zone, a second anti-stress zone and a second exposing zone, the second anti-stress zone is located at a corner of the second disposing zone. The first anti-stress zone and the second anti-stress zone are located at the first corner. An area of the first anti-stress zone is not smaller than that of the second anti-stress zone.

Abstract translation: 具有第一角的半导体结构包括载体，第一保护层，第二保护层和第三保护层。 载体包括具有保护层叠布置区的载体表面。 第一保护层包括具有第一布置区，第一抗应力区和第一曝光区的第一表面，第一抗应力区位于第一布置区的拐角处，第二保护层设置在 第一个处置区。 第二保护层包括具有第二设置区，第二抗应力区和第二曝光区的第二表面，第二抗应力区位于第二处置区的拐角处。 第一个抗应力区和第二个抗应力区位于第一个拐角处。 第一抗应力区域的面积不小于第二抗应力区域的面积。

公开(公告)号：US20140021601A1

公开(公告)日：2014-01-23

申请号：US13644749

申请日：2012-10-04

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chih-Ming Kuo ,  Lung-Hua Ho ,  Shih-Chieh Chang ,  Chia-Yeh Huang ,  Chin-Tang Hsieh

IPC: H01L23/48 ,  H01L21/60

CPC classification number: H01L21/76885 ,  H01L21/4853 ,  H01L23/48 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11903 ,  H01L2224/13006 ,  H01L2224/13016 ,  H01L2224/13023 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A semiconductor manufacturing method includes providing a carrier; forming a first photoresist layer; forming plural core portions; removing the first photoresist layer; forming a second photoresist layer; forming a plurality of connection portions, each of the plurality of connection portions includes a first connection layer and a second connection layer and connects to each of the core portions to form a hybrid bump, wherein each of the first connection layers comprises a base portion, a projecting portion and an accommodating space, each base portion comprises an upper surface, each projecting portion is protruded to the upper surface and located on top of each core portion, each accommodating space is located outside each projecting portion, the second connection layers cover the projecting portions and the upper surfaces, and the accommodating spaces are filled by the second connection layers; removing the second photoresist layer to reveal the hybrid bumps.