公开(公告)号：US20240193331A1

公开(公告)日：2024-06-13

申请号：US18584339

申请日：2024-02-22

Applicant: Altera Corporation

Inventor： Michael Kinsner ,  Byron Sinclair ,  Gregory Nash

IPC: G06F30/33

CPC classification number: G06F30/33

Abstract: An integrated circuit includes configurable logic circuit blocks that are configurable with a first configuration bitstream according to a coarse grained configuration. The coarse grained configuration implements an aggregate circuit structure of the configurable logic circuit blocks. The configurable logic circuit blocks are configurable with a second configuration bitstream according to a fine grained configuration. A total number of the first and the second configuration bits is fewer than a single fine grained configuration bitstream.

公开(公告)号：US20240192983A1

公开(公告)日：2024-06-13

申请号：US18412098

申请日：2024-01-12

Applicant: Altera Corporation

Inventor： Abdel Hafiz Rabi ,  Allen Chen ,  Mark Jonathan Lewis ,  Jiefan Zhang

IPC: G06F9/455 ,  G06F13/28 ,  G06F13/40

CPC classification number: G06F9/45558 ,  G06F13/28 ,  G06F13/4022 ,  G06F2009/45595 ,  G06F2213/0038 ,  G06F2213/28

Abstract: A virtualization platform for Network Functions Virtualization (NFV) is provided. The virtualization platform may include a host processor coupled to an acceleration coprocessor. The acceleration coprocessor may be a reconfigurable integrated circuit to help provide improved flexibility and agility for the NFV. The coprocessor may include multiple virtual function hardware acceleration modules each of which is configured to perform a respective accelerator function. A virtual machine running on the host processor may wish to perform multiple accelerator functions in succession at the coprocessor on a given data. In one suitable arrangement, intermediate data output by each of the accelerator functions may be fed back to the host processor. In another suitable arrangement, the successive function calls may be chained together so that only the final resulting data is fed back to the host processor.

公开(公告)号：US12007929B2

公开(公告)日：2024-06-11

申请号：US17067365

申请日：2020-10-09

Applicant: Intel Corporation

Inventor： Anshuman Thakur ,  Dheeraj Subbareddy ,  MD Altaf Hossain ,  Ankireddy Nalamalpu ,  Mahesh Kumashikar

IPC: G06F13/40

CPC classification number: G06F13/4068

Abstract: A processor having a system on a chip (SOC) architecture comprises one or more central processing units (CPUs) comprising multiple cores. An optical Compute Express Link (CXL) communication path incorporating a logical optical CXL protocol stack path transmits and receives an optical bit stream directly after the link layer, bypassing multiple levels of the CXL protocol stack. A CXL interface controller is connected to the one or more CPUs to enable communication between the CPUs and one or more CXL devices over the optical CXL communication path.

公开(公告)号：US20240113985A1

公开(公告)日：2024-04-04

申请号：US18538386

申请日：2023-12-13

Applicant: Altera Corporation

Inventor： Kenneth Taylor ,  Robert Critchlow

IPC: H04L47/52 ,  H04L47/12 ,  H04L47/6295

CPC classification number: H04L47/527 ,  H04L47/12 ,  H04L47/6295

Abstract: An integrated circuit includes queue circuits for storing packets, a scheduler circuit that schedules the packets received from the queue circuits to be provided in an output, and a traffic manager circuit that disables one of the queue circuits from transmitting any of the packets to the scheduler circuit based at least in part on a bandwidth in the output scheduled for a subset of the packets received from the one of the queue circuits.

公开(公告)号：US20240113014A1

公开(公告)日：2024-04-04

申请号：US18539193

申请日：2023-12-13

Applicant: Altera Corporation

Inventor： Krishna Bharath Kolluru ,  Atul Maheshwari ,  Mahesh Kumashikar ,  Md Altaf Hossain ,  Ankireddy Nalamalpu ,  Jeffrey Chromczak

IPC: H01L23/525 ,  H01L23/528 ,  H01L27/105

CPC classification number: H01L23/525 ,  H01L23/528 ,  H01L27/105

Abstract: An integrated circuit includes first external conductive pads, second external conductive pads, and third external conductive pads. The second external conductive pads are between the first external conductive pads and the third external conductive pads. Repair group circuitry is configurable to shift signal transmission away from one of the first external conductive pads to one of the third external conductive pads if the one of the first external conductive pads has a defect.

公开(公告)号：US20240078211A1

公开(公告)日：2024-03-07

申请号：US18368492

申请日：2023-09-14

Applicant: Altera Corporation

Inventor： David Shippy ,  Martin Langhammer ,  Jeffrey Eastlack

IPC: G06F15/78 ,  G06F9/30 ,  G06F9/38 ,  G06F9/54 ,  G06F13/12 ,  G06F13/28 ,  G06F17/14

CPC classification number: G06F15/7825 ,  G06F9/30036 ,  G06F9/3877 ,  G06F9/3887 ,  G06F9/541 ,  G06F13/124 ,  G06F13/28 ,  G06F17/142

Abstract: An accelerated processor structure on a programmable integrated circuit device includes a processor and a plurality of configurable digital signal processors (DSPs). Each configurable DSP includes a circuit block, which in turn includes a plurality of multipliers. The accelerated processor structure further includes a first bus to transfer data from the processor to the configurable DSPs, and a second bus to transfer data from the configurable DSPs to the processor.

公开(公告)号：US20230418573A1

公开(公告)日：2023-12-28

申请号：US18466589

申请日：2023-09-13

Applicant: Altera Corporation

Inventor： Alan Baker ,  Andrew Chaang Ling ,  Andrei Mihai Hagiescu Miriste

IPC: G06F8/41 ,  G06F8/40 ,  G06F9/54 ,  G06F30/34 ,  G06F30/327

CPC classification number: G06F8/41 ,  G06F8/40 ,  G06F9/54 ,  G06F30/34 ,  G06F30/327 ,  G06F2115/08

Abstract: Systems and methods for dynamically sizing inter-kernel communication channels implemented on an integrated circuit (IC) are provided. Implementation characteristics of the channels, predication, and kernel scheduling imbalances may factor into properly sizing the channels for self-synchronization, resulting in optimized steady-state throughput.

公开(公告)号：US20230289319A1

公开(公告)日：2023-09-14

申请号：US18299662

申请日：2023-04-12

Applicant: Altera Corporation

Inventor： Gary Brian Wallichs ,  Keith Duwel ,  Cora Lynn Mau

IPC: G06F13/42 ,  H04L69/14 ,  G06F5/06

CPC classification number: G06F13/4286 ,  H04L69/14 ,  G06F5/065 ,  H04L49/25

Abstract: Systems and methods are provided for supporting wide-protocol interface across a multi-die interconnect interface. Data signals of a wide-protocol interface are split into a plurality of data streams. A handshake signal is established between a first circuit and a second circuit, whereby the first circuit and second circuit are dies of a multi-die device. The first circuit transmits the plurality of data streams to the second circuit via a plurality of multi-die interconnect channels. Each data stream of the plurality of data streams are compressed based on the handshake signal in order to provide wide-protocol interface with reduced number of required pins.

公开(公告)号：US11669479B2

公开(公告)日：2023-06-06

申请号：US17711860

申请日：2022-04-01

Applicant: Altera Corporation

Inventor： Huy Ngo ,  Keith Duwel ,  David W. Mendel

IPC: G06F13/40 ,  G06F13/42 ,  G06F5/06

CPC classification number: G06F13/4022 ,  G06F5/065 ,  G06F13/4018 ,  G06F13/4291 ,  G06F2205/067

Abstract: Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with the EMIB interconnects. The adapter circuitry may include FIFO buffer circuits operable in a 1× mode or 2× mode and configurable in a phase-compensation mode, a clock-compensation mode, an elastic mode, and a register bypass mode to help support a variety of communications protocols with different data width and clocking requirements. The adapter circuitry may also include boundary alignment circuitry for reconstructing (de)compressed data streams.

公开(公告)号：US11520394B2

公开(公告)日：2022-12-06

申请号：US15889566

申请日：2018-02-06

Applicant: Altera Corporation

Inventor： Krishnan Venkataraman

IPC: G06F1/00 ,  G06F1/32 ,  G06F1/329

Abstract: Systems and methods are provided for reducing power consumption of a multi-die device, such as a network processor FPGA (npFPGA). The multi-die device may include hardware resources such as FPGA dies, which may be coupled to NIC dies and/or memory dies. Power consumption of the multi-die device may be reduced by monitoring usage of hardware resources in the multi-die device, identifying hardware resources that are not in use, and gating power to the identified hardware resources. The status of processing elements (PEs) in the multi-die device may be tracked in a PE state table. Based on the PE state table, tasks from a task queue may be assigned to one or more processing elements.