公开(公告)号：US20040245567A1

公开(公告)日：2004-12-09

申请号：US10860112

申请日：2004-06-04

Applicant: Matsushita Elec. Ind. Co. Ltd.

Inventor： Toshiaki Kawasaki

IPC: G11C011/34

CPC classification number: G11C16/0416 ,  G11C2216/10 ,  H01L27/115 ,  H01L27/11558 ,  Y10S257/909

Abstract: In a memory cell, the substrate contact region of an NMOS transistor and the well contact region of a PMOS transistor are arranged perpendicularly to a floating gate. In a cell array, the memory cell and another memory cell arranged axisymmetrically with respect to the memory cell are alternately arranged in the column direction to constitute a sub array, and the sub arrays arranged in the column direction are arranged in parallel or axisymmetically in the row direction. With this arrangement, the substrate contact region, the well contact region, and the diffusion region of the PMOS transistor can be shared between the adjacent memory cells, thereby reducing the area of the cell array.

Abstract translation: 在存储单元中，NMOS晶体管的衬底接触区域和PMOS晶体管的阱接触区域垂直于浮置栅极布置。 在单元阵列中，存储单元和相对于存储单元轴对称布置的另一个存储单元在列方向上交替布置以构成子阵列，并且沿列方向排列的子阵列平行或轴对称地布置在 行方向。 利用这种布置，可以在相邻的存储单元之间共享衬底接触区域，阱接触区域和PMOS晶体管的扩散区域，从而减小单元阵列的面积。

公开(公告)号：US20040173842A1

公开(公告)日：2004-09-09

申请号：US10798481

申请日：2004-03-12

Inventor： Akira Goda ,  Riichiro Shirota ,  Kazuhiro Shimizu ,  Hiroaki Hazama ,  Hirohisa Iizuka ,  Seiichi Aritome ,  Wakako Moriyama

IPC: H01L021/336

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11529 ,  H01L27/11543 ,  Y10S257/909

Abstract: A nonvolatile semiconductor memory device having a memory cell portion and peripheral circuit portion is disclosed. The nonvolatile semiconductor memory device has peripheral transistors formed in the peripheral circuit portion of a silicon substrate and cell transistors formed in the memory cell portion of the silicon substrate. The gate length of the cell transistor is shorter than the gate length of the peripheral transistor. Further, the nonvolatile semiconductor memory device has a silicon nitride film selectively formed on the memory cell portion. The silicon nitride film covers the cell transistors.

Abstract translation: 公开了一种具有存储单元部分和外围电路部分的非易失性半导体存储器件。 非易失性半导体存储器件具有形成在硅衬底的外围电路部分中的外围晶体管和形成在硅衬底的存储单元部分中的单元晶体管。 单元晶体管的栅极长度短于外围晶体管的栅极长度。 此外，非易失性半导体存储器件具有选择性地形成在存储单元部分上的氮化硅膜。 氮化硅膜覆盖电池晶体管。

公开(公告)号：US20040005738A1

公开(公告)日：2004-01-08

申请号：US10601351

申请日：2003-06-23

Applicant: Hyundai Electronics America

Inventor： Harold S. Crafts

IPC: H01L021/82

CPC classification number: H01L27/0207 ,  H01L27/11807 ,  H01L2924/0002 ,  Y10S257/909 ,  H01L2924/00

Abstract: The invention concerns integrated circuits in which a MACRO is embedded in a standard cell array. One level of metal is devoted exclusively to non-local interconnect, and a layer of polysilicon is devoted to local interconnect, thereby saving significant space.

公开(公告)号：US06605499B1

公开(公告)日：2003-08-12

申请号：US09704115

申请日：2000-11-01

Applicant: Harold S. Crafts

Inventor： Harold S. Crafts

IPC: H01L21331

CPC classification number: H01L27/0207 ,  H01L27/11807 ,  H01L2924/0002 ,  Y10S257/909 ,  H01L2924/00

Abstract: The invention concerns integrated circuits in which a MACRO is embedded in a standard cell array. One level of metal is devoted exclusively to non-local interconnect, and a layer of polysilicon is devoted to local interconnect, thereby saving significant space.

Abstract translation: 本发明涉及其中MACRO嵌入在标准单元阵列中的集成电路。 一层金属专用于非局部互连，一层多晶硅专用于局部互连，从而节省了大量的空间。

公开(公告)号：US06601199B1

公开(公告)日：2003-07-29

申请号：US09405128

申请日：1999-09-24

Applicant: Ryo Fukuda ,  Hironori Banba ,  Toshimasa Namekawa ,  Shinji Miyano

Inventor： Ryo Fukuda ,  Hironori Banba ,  Toshimasa Namekawa ,  Shinji Miyano

IPC: G01R3128

CPC classification number: G01R31/3167 ,  G01R31/318505 ,  Y10S257/909

Abstract: A plurality of memory macros are laid out in a semiconductor chip. Macro ID generation circuits generate macro IDs for identifying the memory macros, and have different layouts. These macro ID generation circuits are arranged outside the memory macros in the semiconductor chip, so that test control blocks in the memory macros can use the same layouts between all the memory macros to reduce the design load.

Abstract translation: 多个存储器宏布置在半导体芯片中。 宏ID生成电路生成用于识别存储宏的宏ID，并具有不同的布局。 这些宏ID生成电路被布置在半导体芯片中的存储器宏之外，使得存储器宏中的测试控制块可以在所有存储器宏之间使用相同的布局来减少设计负载。

公开(公告)号：US06476425B1

公开(公告)日：2002-11-05

申请号：US09509307

申请日：2000-06-22

Applicant: Yoshiteru Ono

Inventor： Yoshiteru Ono

IPC: H01L27108

CPC classification number: H01L27/11803 ,  H01L27/0207 ,  H01L27/11807 ,  Y10S257/909 ,  Y10S438/982

Abstract: A placing and wiring method for a master slice type semiconductor integrated circuit is provided. The method is conducted by an automatic placing and routing apparatus with respect to a master slice 100 having a plurality of basic cells 110 formed in a matrix, in which first and second power source wirings 170 and 171 that traverse the plurality of basic cells 110 are connected to a plurality of signal wirings that are formed along a vertical direction to provide connections within each of the plurality of basic cells 110 and/or between the plurality of basic cells 110. The method includes: a first step of registering in the automatic pacing and routing apparatus definitions of effective pin positions A1-A14, B2-B13 and C1-C14; a second step of registering a net list in the automatic placing and routing apparatus; and a third step of determining the placement of pin positions and wiring routes, based on data for the definitions of the effective pin positions and the net list. The registered effective pin positions are provided on lattice grids 120, located inside and outside a region between the first and second power source wirings 170 and 171. In the circuit wired according to the definitions, contacts with respect to the drains are provided inside and outside the region between the first and second power source wirings 170 and 171, and the signal wirings do not cross the power source wirings.

Abstract translation: 提供了一种用于主片式半导体集成电路的放置和布线方法。 该方法通过自动放置和路由装置对具有矩阵形成的多个基本单元110的主切片100进行，其中穿过多个基本单元110的第一和第二电源布线170和171是 连接到沿着垂直方向形成的多个信号布线，以提供多个基本单元110内和/或多个基本单元110之间的连接。该方法包括：第一步，在自动起搏 以及有效引脚位置A1-A14，B2-B13和C1-C14的路由设备定义; 在自动放置和路由设备中注册网络列表的第二步骤; 以及基于有效引脚位置和网络列表的定义的数据来确定引脚位置和布线路线的布置的第三步骤。 注册的有效销位置设置在位于第一和第二电源配线170和171之间的区域内外的格栅120上。在根据定义布线的电路中，相对于排水口的接触设置在内部和外部 第一和第二电源布线170和171之间的区域，并且信号布线不与电源布线交叉。

公开(公告)号：US20020142512A1

公开(公告)日：2002-10-03

申请号：US09821521

申请日：2001-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.,

Inventor： Ssu-Pin Ma ,  Yen-Shih Ho

IPC: H01L021/00

CPC classification number: H01L24/05 ,  H01L23/5227 ,  H01L23/645 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01067 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/30105 ,  H01L2924/30107 ,  Y10S257/909 ,  H01L2224/48824 ,  H01L2924/00 ,  H01L2224/48744

Abstract: Within a method for fabricating a microelectronic fabrication there is first provided a substrate. There is then formed over the substrate a spirally patterned conductor layer which terminates in a microelectronic structure within the center of the spirally patterned conductor layer. The spirally patterned conductor layer forms a planar spiral inductor, and the microelectronic structure formed within the center of the spirally patterned conductor layer further comprises a series of electrically interconnected sub-patterns. The method contemplates a microelectronic fabrication fabricated in accord with the method. The microelectronic fabrication is fabricated with optimal performance while occupying minimal microelectronic substrate area.

Abstract translation: 在微电子制造的制造方法中，首先提供基板。 然后在衬底上形成螺旋状图案化的导体层，其终止于螺旋形图案化的导体层的中心内的微电子结构。 螺旋形图案的导体层形成平面螺旋电感器，并且形成在螺旋图案化导体层的中心内的微电子结构还包括一系列电互连子图案。 该方法考虑了根据该方法制造的微电子制造。 微电子制造以最佳性能制造，同时占据最小的微电子衬底面积。

公开(公告)号：US06256604B1

公开(公告)日：2001-07-03

申请号：US09120999

申请日：1998-07-23

Applicant: Tomoaki Yabe ,  Shinji Miyano

Inventor： Tomoaki Yabe ,  Shinji Miyano

IPC: G06F1750

CPC classification number: G11C5/025 ,  G11C7/1006 ,  G11C7/18 ,  G11C2207/104 ,  Y10S257/909

Abstract: In a structure and a designing method of a memory integrated with a logic, a memory macro comprises L memory array blocks 1-1, 1-2, . . . 1-L each including memory cell arrays each with a storage capacity of K bits and sense amplifiers. Memory array power source driver blocks 4-1, 4-2, . . . 4-L each including a circuit for generating a driver power source which drives a sense amplifier are arranged in a corresponding manner to memory array blocks 1-1, 1-2, . . . 1-L. The memory array blocks 1-1, 1-2, . . . 1-L are arranged along a column direction in an adjacent manner to one another and DQ line pairs extending along a column direction are arranged on the memory array blocks 1-1, 1-2, . . . 1-L. Source line blocks 6a-L, 6b-L, 7a, 7b, 8a, 8b are arranged at an end of the memory array blocks in a row direction. According to such a design, short design turnaround for design and shrinkage of occupying area of a memory macro can be realized.

Abstract translation: 在与逻辑集成的存储器的结构和设计方法中，存储器宏包括L个存储器阵列块1-1,1-2。 。 。 1-L每个包括存储单元阵列，每个存储单元阵列具有K位的存储容量和读出放大器。 内存阵列电源驱动程序块4-1,4-2，。 。 。 包括用于产生驱动读出放大器的驱动器电源的电路的4-L以对应于存储器阵列块1-1,1-2的方式布置。 。 。 1-L。 存储器阵列块1-1,1-2，...。 。 。 1-L沿着列方向彼此相邻布置，并且沿着列方向延伸的DQ线对布置在存储器阵列块1-1,1-2上。 。 。 1-L。 源极线块6a-L，6b-L，7a，7b，8a，8b布置在存储器阵列块的行方向的一端。 根据这样的设计，可以实现存储器宏的占用面积的设计和收缩的简短设计周转。

公开(公告)号：US5656850A

公开(公告)日：1997-08-12

申请号：US396542

申请日：1995-03-01

Applicant: Ashok Kapoor

Inventor： Ashok Kapoor

IPC: H01L27/118

CPC classification number: H01L27/11803 ,  Y10S257/909

Abstract: A microelectronic integrated circuit includes a semiconductor substrate, and a plurality of microelectronic devices formed on the substrate. Each device has a periphery defined by a hexagon, and includes an active area formed within the periphery. A first terminal and a second terminal are formed in the active area adjacent to edges of the hexagon that are separated by another edge. First to third gates are formed between the first and second terminals, and have gate terminals formed outside the active area adjacent to other edges of the hexagon. The power supply connections to the first and second terminals, the conductivity type (NMOS or PMOS), and the addition of a pull-up or a pull-down resistor is selected for each device to provide a desired AND, NAND, OR or NOR function. The devices are interconnected using three direction routing based on hexagonal geometry.

Abstract translation: 微电子集成电路包括半导体衬底和形成在衬底上的多个微电子器件。 每个装置具有由六边形限定的周边，并且包括在周边内形成的有效区域。 第一端子和第二端子形成在与另一边缘分离的六边形边缘相邻的有源区域中。 第一至第三栅极形成在第一和第二端子之间，并且具有形成在与六边形的其它边缘相邻的有源区域外部的栅极端子。 为每个器件选择与第一和第二端子的电源连接，导电类型（NMOS或PMOS）以及上拉或下拉电阻的添加，以提供所需的AND，NAND，或或NOR 功能。 这些设备使用基于六边形几何的三向路由进行互连。

公开(公告)号：US5635737A

公开(公告)日：1997-06-03

申请号：US574496

申请日：1995-12-19

Applicant: Patrick Yin

Inventor： Patrick Yin

IPC: H01L27/118 ,  H01L27/10

CPC classification number: H01L27/11807 ,  Y10S257/909

Abstract: A gate array architecture is disclosed that utilizes significantly less silicon area than the prior art. The core cell includes a four transistor arrangement in which a substrate tap is located adjacent to the transistor pair. This provides for a more "symmetric" cell array than those in the prior art. Through the placement of the taps outside of the transistors the power line connections can be routed in a simple and efficient manner. The architecture includes an extension portion in the contact region of the cell to further reduce wiring complexity. In addition the gate array architecture mirrors pairs of transistor columns to allow for the sharing of substrate taps between pairs of columns. This mirroring feature further reduces routing complexity. The architecture further includes a plurality of probe lines that are located within the architecture to facilitate testability of the outputs of the architecture.

Abstract translation: 公开了一种门阵列结构，其利用比现有技术明显更少的硅面积。 核心单元包括四晶体管布置，其中衬底抽头位于与晶体管对相邻的位置。 这提供了比现有技术中更“对称”的单元阵列。 通过在晶体管外放置抽头，电力线连接可以以简单有效的方式布线。 该架构在单元的接触区域中包括延伸部分，以进一步降低布线复杂性。 此外，门阵列架构镜像成对的晶体管列以允许共享列对之间的衬底抽头。 这种镜像功能进一步降低了路由复杂度。 架构还包括位于架构内的多个探测线，以便于架构的输出的可测试性。