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    Symmetrical multi-layer metal logic array with continuous substrate taps and extension portions for increased gate density
    1.
    发明授权
    Symmetrical multi-layer metal logic array with continuous substrate taps and extension portions for increased gate density 失效

    公开(公告)号：US5493135A

    公开(公告)日：1996-02-20

    申请号：US376404

    申请日：1995-01-23

    Applicant: Patrick Yin

    Inventor： Patrick Yin

    IPC: H01L21/82 ,  H01L27/118 ,  H01L27/10 ,  H01L27/02

    CPC classification number: H01L27/11803 ,  H01L27/11807

    Abstract: A gate array architecture is disclosed that utilizes significantly less silicon area than the prior art. The core cell includes a four transistor arrangement in which a substrate tap is located adjacent to the transistor pair. This provides for a more "symmetric" cell array than those in the prior art. Through the placement of the taps outside of the transistors the power line connections can be routed in a simple and efficient manner. The architecture includes an extension portion in the contact region of the cell to further reduce wiring complexity. In addition the gate array architecture mirrors pairs of transistor columns to allow for the sharing of substrate taps between pairs of columns. This mirroring feature further reduces routing complexity.

    Method and system for allowing an integrated circuit to be portably generated from one manufacturing process to another
    3.
    发明授权
    Method and system for allowing an integrated circuit to be portably generated from one manufacturing process to another 失效
    允许将集成电路从一个制造过程可移植地生成到另一个制造过程的方法和系统

    公开(公告)号：US06298469B1

    公开(公告)日：2001-10-02

    申请号：US08688218

    申请日：1996-07-29

    Applicant: Patrick Yin

    Inventor： Patrick Yin

    IPC: G06F1750

    CPC classification number: G06F17/5068

    Abstract: A system and method is provided which generates integrated circuits for integrated circuits that are portable from process to process. Information generated from an integrated circuit manufactured on a first process is utilized in combination with the parameters of a subsequent manufacturing process to obtain an integrated circuit based upon that second manufacturing process. Through this system and method a particular integrated circuit design is portable from process to process.

    Abstract translation: 提供了一种系统和方法，其生成从过程到处理可移植的集成电路的集成电路。 从在第一处理中制造的集成电路产生的信息与随后的制造过程的参数结合使用以基于该第二制造过程获得集成电路。 通过这种系统和方法，特定的集成电路设计可以从过程到处理。

    Low leakage output driver circuit which can be utilized in a multi-voltage source
    5.
    发明授权
    Low leakage output driver circuit which can be utilized in a multi-voltage source 失效
    低泄漏输出驱动电路，可用于多电压源

    公开(公告)号：US5723992A

    公开(公告)日：1998-03-03

    申请号：US545158

    申请日：1995-10-19

    Applicant: Patrick Yin ,  Craig S. Thrower

    Inventor： Patrick Yin ,  Craig S. Thrower

    IPC: H03K19/003 ,  H03K17/687 ,  H03K17/16

    CPC classification number: H03K19/00315

    Abstract: An improved output driver circuit is disclosed which can be utilized when a plurality of voltage potentials are present. The output driver circuit comprises a first pull-up transistor coupled to a first voltage potential, a second pull-down transistor coupled to a second voltage potential, and a pad member coupled to the first pull-up and second pull-down transistor. The driver circuit further includes a circuit means which is coupled to the pad member and the first pull-up transistor. Accordingly, through this arrangement, the circuit substantially reduces the leakage through the first pull-up transistor when the pad member is coupled to a third voltage potential. An output driver circuit in accordance with the present invention, can be utilized in an integrated circuit environment where multiple voltages such as 3.3 volts and 5 volts are present and the output driver circuit will operate effectively because the leakage path normally associated with such circuits is substantially minimized.

    Abstract translation: 公开了一种改进的输出驱动器电路，其可以在存在多个电压电位时使用。 输出驱动器电路包括耦合到第一电压电位的第一上拉晶体管，耦合到第二电压电位的第二下拉晶体管，以及耦合到第一上拉和第二下拉晶体管的焊盘构件。 驱动器电路还包括耦合到焊盘构件和第一上拉晶体管的电路装置。 因此，通过这种布置，当焊盘构件耦合到第三电压电位时，电路基本上减少通过第一上拉晶体管的泄漏。 根据本发明的输出驱动器电路可以用在其中存在多个电压（例如3.3伏特和5伏特）的集成电路环境中，并且输出驱动器电路将有效地工作，因为通常与这种电路相关联的泄漏路径基本上是 最小化。

    Symmetrical multi-layer metal logic array with continuous substrate taps
    6.
    发明授权
    Symmetrical multi-layer metal logic array with continuous substrate taps 失效
    具有连续衬底抽头的对称多层金属逻辑阵列

    公开(公告)号：US5404034A

    公开(公告)日：1995-04-04

    申请号：US194729

    申请日：1994-02-10

    Applicant: Patrick Yin

    Inventor： Patrick Yin

    IPC: H01L21/82 ,  H01L27/118 ,  H01L27/10

    CPC classification number: H01L27/11803

    Abstract: A gate array architecture is disclosed that utilizes significantly less silicon area than the prior art. The core cell includes a four transistor arrangement in which a substrate tap is located adjacent to the transistor pair. This provides for a more "symmetric" cell array than those in the prior art. Through the placement of the taps outside of the transistors the power line connections can be routed in a simple and efficient manner. In addition the gate array architecture mirrors pairs of transistor columns to allow for the sharing of substrate taps between pairs of columns. This mirroring feature further reduces routing complexity.

    Abstract translation: 公开了一种门阵列结构，其利用比现有技术明显更少的硅面积。 核心单元包括四晶体管布置，其中衬底抽头位于与晶体管对相邻的位置。 这提供了比现有技术中更“对称”的单元阵列。 通过在晶体管外放置抽头，电力线连接可以以简单有效的方式布线。 此外，门阵列架构镜像成对的晶体管列以允许共享列对之间的衬底抽头。 这种镜像功能进一步降低了路由复杂度。

    Cell architecture for mixed signal applications
    7.
    发明授权
    Cell architecture for mixed signal applications 失效
    用于混合信号应用的单元架构

    公开(公告)号：US5701021A

    公开(公告)日：1997-12-23

    申请号：US574497

    申请日：1995-12-19

    Applicant: Patrick Yin

    Inventor： Patrick Yin

    IPC: H01L27/118 ,  H01L27/092

    CPC classification number: H01L27/11803

    Abstract: A cell architecture for mixed signal applications is disclosed that utilizes significantly less silicon area than the prior art. The core cell includes a transistor arrangement in which substrate taps are located adjacent to the transistor pairs. This provides for a more "symmetric" cell array than those in the prior art. Through the placement of the taps outside of the transistors the power line connections can be routed in a simple and efficient manner. The architecture includes an extension portion in the contact region of the cell to further reduce wiring complexity. In addition the gate array architecture mirrors pairs of transistor columns to allow for the sharing of substrate taps between pairs of columns. This mirroring feature further reduces routing complexity. The cell architecture includes a substrate tap area that allows for the accommodation of a plurality of electrically isolated metal lines.

    Abstract translation: 公开了一种用于混合信号应用的电池结构，其利用比现有技术明显更少的硅面积。 核心单元包括其中衬底抽头位于晶体管对附近的晶体管布置。 这提供了比现有技术中更“对称”的单元阵列。 通过在晶体管外放置抽头，电力线连接可以以简单有效的方式布线。 该架构在单元的接触区域中包括延伸部分，以进一步降低布线复杂性。 此外，门阵列架构镜像成对的晶体管列以允许共享列对之间的衬底抽头。 这种镜像功能进一步降低了路由复杂度。 电池结构包括允许容纳多个电隔离金属线的衬底抽头区域。

    Symmetrical multi-layer metal logic array with extension portions for increased gate density and a testability area
    8.
    发明授权
    Symmetrical multi-layer metal logic array with extension portions for increased gate density and a testability area 失效
    具有扩展部分的对称多层金属逻辑阵列，用于增加栅极密度和可测试性区域

    公开(公告)号：US5635737A

    公开(公告)日：1997-06-03

    申请号：US574496

    申请日：1995-12-19

    Applicant: Patrick Yin

    Inventor： Patrick Yin

    IPC: H01L27/118 ,  H01L27/10

    CPC classification number: H01L27/11807 ,  Y10S257/909

    Abstract: A gate array architecture is disclosed that utilizes significantly less silicon area than the prior art. The core cell includes a four transistor arrangement in which a substrate tap is located adjacent to the transistor pair. This provides for a more "symmetric" cell array than those in the prior art. Through the placement of the taps outside of the transistors the power line connections can be routed in a simple and efficient manner. The architecture includes an extension portion in the contact region of the cell to further reduce wiring complexity. In addition the gate array architecture mirrors pairs of transistor columns to allow for the sharing of substrate taps between pairs of columns. This mirroring feature further reduces routing complexity. The architecture further includes a plurality of probe lines that are located within the architecture to facilitate testability of the outputs of the architecture.

    Abstract translation: 公开了一种门阵列结构，其利用比现有技术明显更少的硅面积。 核心单元包括四晶体管布置，其中衬底抽头位于与晶体管对相邻的位置。 这提供了比现有技术中更“对称”的单元阵列。 通过在晶体管外放置抽头，电力线连接可以以简单有效的方式布线。 该架构在单元的接触区域中包括延伸部分，以进一步降低布线复杂性。 此外，门阵列架构镜像成对的晶体管列以允许共享列对之间的衬底抽头。 这种镜像功能进一步降低了路由复杂度。 架构还包括位于架构内的多个探测线，以便于架构的输出的可测试性。

    Symmetrical multi-layer metal logic array with continuous substrate taps and extension portions for increased gate density
    9.
    发明授权
    Symmetrical multi-layer metal logic array with continuous substrate taps and extension portions for increased gate density 失效
    具有连续衬底抽头和扩展部分的对称多层金属逻辑阵列，用于增加栅极密度

    公开(公告)号：US5384472A

    公开(公告)日：1995-01-24

    申请号：US112680

    申请日：1993-08-26

    Applicant: Patrick Yin

    Inventor： Patrick Yin

    IPC: H01L21/82 ,  H01L27/118 ,  H01L22/10 ,  H01L27/02

    CPC classification number: H01L27/11803 ,  H01L27/11807

    Abstract: A gate array architecture is disclosed that utilizes significantly less silicon area than the prior art. The core cell includes a four transistor arrangement in which a substrate tap is located adjacent to the transistor pair. This provides for a more "symmetric" cell array than those in the prior art. Through the placement of the taps outside of the transistors the power line connections can be routed in a simple and efficient manner. The architecture includes an extension portion in the contact region of the cell to further reduce wiring complexity. In addition the gate array architecture mirrors pairs of transistor columns to allow for the sharing of substrate taps between pairs of columns. This mirroring feature further reduces routing complexity.

    Abstract translation: 公开了一种门阵列结构，其利用比现有技术明显更少的硅面积。 核心单元包括四晶体管布置，其中衬底抽头位于与晶体管对相邻的位置。 这提供了比现有技术中更“对称”的单元阵列。 通过在晶体管外放置抽头，电力线连接可以以简单有效的方式布线。 该架构在单元的接触区域中包括延伸部分，以进一步降低布线复杂性。 此外，门阵列架构镜像成对的晶体管列以允许共享列对之间的衬底抽头。 这种镜像功能进一步降低了路由复杂度。

    Tri-state CMOS driver having reduced gate delay
    10.
    发明授权
    Tri-state CMOS driver having reduced gate delay 失效
    减少门延迟的三态CMOS驱动器

    公开(公告)号：US4465945A

    公开(公告)日：1984-08-14

    申请号：US414743

    申请日：1982-09-03

    Applicant: Patrick Yin

    Inventor： Patrick Yin

    IPC: H03K19/0175 ,  H03K19/094 ,  H03K19/017 ,  H03K19/20

    CPC classification number: H03K19/09425

    Abstract: A Tri-State circuit element is constructed which is uniquely suited for use in large scale integrated circuit devices wherein a relatively large number of such Tri-State circuits are utilized to drive other circuitry contained within the integrated circuit device. One embodiment of a Tri-State circuit is constructed utilizing a single NAND gate (73), a single inverter (74), a single P channel transistor (76), and two N channel transistors (77, 78) yielding a circuit having a propagation delay of only two gate delays and requiring a total of only nine transistors. Another embodiment of this invention is a Tri-State circuit constructed utilizing a single NOR gate (84), a single inverter (83), a single N channel transistor (88), and two P channel transistors (86, 87). In this embodiment of my invention, a total of nine MOS transistors are required, and the propagation delay between the input terminal and the output terminal is equal to two gate delays.

    Abstract translation: 构造了三态电路元件，其特别适用于大规模集成电路器件，其中使用相对大量的这种三态电路来驱动集成电路器件中所包含的其它电路。 利用单个NAND门（73），单个逆变器（74），单个P沟道晶体管（76）和两个N沟道晶体管（77,78）构成三态电路的一个实施例，产生具有 只有两个门延迟的传播延迟和总共只有九个晶体管。 本发明的另一个实施例是利用单个NOR门（84），单个逆变器（83），单个N沟道晶体管（88）和两个P沟道晶体管（86,87）构成的三态电路。 在本发明的这个实施例中，需要总共9个MOS晶体管，并且输入端和输出端之间的传播延迟等于两个门延迟。

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