公开(公告)号：US5723992A

公开(公告)日：1998-03-03

申请号：US545158

申请日：1995-10-19

Applicant: Patrick Yin ,  Craig S. Thrower

Inventor： Patrick Yin ,  Craig S. Thrower

IPC: H03K19/003 ,  H03K17/687 ,  H03K17/16

CPC classification number: H03K19/00315

Abstract: An improved output driver circuit is disclosed which can be utilized when a plurality of voltage potentials are present. The output driver circuit comprises a first pull-up transistor coupled to a first voltage potential, a second pull-down transistor coupled to a second voltage potential, and a pad member coupled to the first pull-up and second pull-down transistor. The driver circuit further includes a circuit means which is coupled to the pad member and the first pull-up transistor. Accordingly, through this arrangement, the circuit substantially reduces the leakage through the first pull-up transistor when the pad member is coupled to a third voltage potential. An output driver circuit in accordance with the present invention, can be utilized in an integrated circuit environment where multiple voltages such as 3.3 volts and 5 volts are present and the output driver circuit will operate effectively because the leakage path normally associated with such circuits is substantially minimized.

Abstract translation: 公开了一种改进的输出驱动器电路，其可以在存在多个电压电位时使用。 输出驱动器电路包括耦合到第一电压电位的第一上拉晶体管，耦合到第二电压电位的第二下拉晶体管，以及耦合到第一上拉和第二下拉晶体管的焊盘构件。 驱动器电路还包括耦合到焊盘构件和第一上拉晶体管的电路装置。 因此，通过这种布置，当焊盘构件耦合到第三电压电位时，电路基本上减少通过第一上拉晶体管的泄漏。 根据本发明的输出驱动器电路可以用在其中存在多个电压（例如3.3伏特和5伏特）的集成电路环境中，并且输出驱动器电路将有效地工作，因为通常与这种电路相关联的泄漏路径基本上是 最小化。

公开(公告)号：US5151622A

公开(公告)日：1992-09-29

申请号：US609836

申请日：1990-11-06

Applicant: Craig S. Thrower ,  King C. Wang

Inventor： Craig S. Thrower ,  King C. Wang

IPC: H03K19/017 ,  H03K19/0185

CPC classification number: H03K19/018521 ,  H03K19/01721

Abstract: A TTL to CMOS input buffer circuit is provided which includes a level shifting circuit including an input terminal and an output node for receiving at the input terminal an input signal at a TTL logic voltage level and for providing at the output node an output signal at a CMOS logic voltage level, the output signal being a logically inverted version of the input signal; and a first circuit for speeding a transition of the output signal from a low CMOS voltage level to a high CMOS voltage level; and a second circuit for preventing the first circuit from interfering with a transition of the output signal from the high CMOS voltage level to the low CMOS voltage level.

Abstract translation: 提供TTL至CMOS输入缓冲电路，其包括电平移位电路，该电平移位电路包括输入端子和输出节点，用于在输入端子处以TTL逻辑电压电平接收输入信号，并在输出节点处提供输出信号 CMOS逻辑电压电平，输出信号为输入信号的逻辑反转版本; 以及用于加速来自低CMOS电压电平的输出信号到高CMOS电压电平的转换的第一电路; 以及用于防止第一电路干扰输出信号从高CMOS电压电平向低CMOS电压电平的转变的第二电路。