公开(公告)号：US5151622A

公开(公告)日：1992-09-29

申请号：US609836

申请日：1990-11-06

Applicant: Craig S. Thrower ,  King C. Wang

Inventor： Craig S. Thrower ,  King C. Wang

IPC: H03K19/017 ,  H03K19/0185

CPC classification number: H03K19/018521 ,  H03K19/01721

Abstract: A TTL to CMOS input buffer circuit is provided which includes a level shifting circuit including an input terminal and an output node for receiving at the input terminal an input signal at a TTL logic voltage level and for providing at the output node an output signal at a CMOS logic voltage level, the output signal being a logically inverted version of the input signal; and a first circuit for speeding a transition of the output signal from a low CMOS voltage level to a high CMOS voltage level; and a second circuit for preventing the first circuit from interfering with a transition of the output signal from the high CMOS voltage level to the low CMOS voltage level.

Abstract translation: 提供TTL至CMOS输入缓冲电路，其包括电平移位电路，该电平移位电路包括输入端子和输出节点，用于在输入端子处以TTL逻辑电压电平接收输入信号，并在输出节点处提供输出信号 CMOS逻辑电压电平，输出信号为输入信号的逻辑反转版本; 以及用于加速来自低CMOS电压电平的输出信号到高CMOS电压电平的转换的第一电路; 以及用于防止第一电路干扰输出信号从高CMOS电压电平向低CMOS电压电平的转变的第二电路。