公开(公告)号：US5384472A

公开(公告)日：1995-01-24

申请号：US112680

申请日：1993-08-26

Applicant: Patrick Yin

Inventor： Patrick Yin

IPC: H01L21/82 ,  H01L27/118 ,  H01L22/10 ,  H01L27/02

CPC classification number: H01L27/11803 ,  H01L27/11807

Abstract: A gate array architecture is disclosed that utilizes significantly less silicon area than the prior art. The core cell includes a four transistor arrangement in which a substrate tap is located adjacent to the transistor pair. This provides for a more "symmetric" cell array than those in the prior art. Through the placement of the taps outside of the transistors the power line connections can be routed in a simple and efficient manner. The architecture includes an extension portion in the contact region of the cell to further reduce wiring complexity. In addition the gate array architecture mirrors pairs of transistor columns to allow for the sharing of substrate taps between pairs of columns. This mirroring feature further reduces routing complexity.

Abstract translation: 公开了一种门阵列结构，其利用比现有技术明显更少的硅面积。 核心单元包括四晶体管布置，其中衬底抽头位于与晶体管对相邻的位置。 这提供了比现有技术中更“对称”的单元阵列。 通过在晶体管外放置抽头，电力线连接可以以简单有效的方式布线。 该架构在单元的接触区域中包括延伸部分，以进一步降低布线复杂性。 此外，门阵列架构镜像成对的晶体管列以允许共享列对之间的衬底抽头。 这种镜像功能进一步降低了路由复杂度。