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    Master slice type semiconductor integrated circuit and method for designing the same
    2.
    发明授权
    Master slice type semiconductor integrated circuit and method for designing the same 失效
    主切片式半导体集成电路及其设计方法

    公开(公告)号：US06844576B2

    公开(公告)日：2005-01-18

    申请号：US10232119

    申请日：2002-08-30

    Applicant: Yoshiteru Ono

    Inventor： Yoshiteru Ono

    IPC: H01L27/02 ,  H01L27/10 ,  H01L27/108 ,  H01L27/118

    CPC classification number: H01L27/11803 ,  H01L27/0207 ,  H01L27/11807 ,  Y10S257/909 ,  Y10S438/982

    Abstract: A placing and wiring method for a master slice type semiconductor integrated circuit is provided. The method is conducted by an automatic placing and routing apparatus with respect to a master slice 100 having a plurality of basic cells 110 formed in a matrix, in which first and second power source wirings 170 and 171 that traverse the plurality of basic cells 110 are connected to a plurality of signal wirings that are formed along a vertical direction to provide connections within each of the plurality of basic cells 110 and/or between the plurality of basic cells 110. The method includes: a first step of registering in the automatic pacing and routing apparatus definitions of effective pin positions A1-A14, B2-B13 and C1-C14; a second step of registering a net list in the automatic placing and routing apparatus; and a third step of determining the placement of pin positions and wiring routes, based on data for the definitions of the effective pin positions and the net list. The registered effective pin positions are provided on lattice grids 120, located inside and outside a region between the first and second power source wirings 170 and 171. In the circuit wired according to the definitions, contacts with respect to the drains are provided inside and outside the region between the first and second power source wirings 170 and 171, and the signal wirings do not cross the power source wirings.

    Abstract translation: 提供了一种用于主片式半导体集成电路的放置和布线方法。 该方法通过自动放置和路由装置对具有矩阵形成的多个基本单元110的主切片100进行，其中穿过多个基本单元110的第一和第二电源布线170和171是 连接到沿着垂直方向形成的多个信号布线，以提供多个基本单元110内和/或多个基本单元110之间的连接。该方法包括：第一步，在自动起搏 以及有效引脚位置A1-A14，B2-B13和C1-C14的路由设备定义; 在自动放置和路由设备中注册网络列表的第二步骤; 以及基于有效引脚位置和网络列表的定义的数据来确定引脚位置和布线路线的布置的第三步骤。 注册的有效销位置设置在位于第一和第二电源配线170和171之间的区域内外的格栅120上。在根据定义布线的电路中，相对于排水口的接触设置在内部和外部 第一和第二电源布线170和171之间的区域，并且信号布线不与电源布线交叉。

    Method for manufacturing semiconductor integrated circuit
    3.
    发明授权
    Method for manufacturing semiconductor integrated circuit 失效
    半导体集成电路制造方法

    公开(公告)号：US06720214B2

    公开(公告)日：2004-04-13

    申请号：US09902267

    申请日：2001-07-11

    Applicant: Yoshiteru Ono

    Inventor： Yoshiteru Ono

    IPC: H01L218238

    CPC classification number: H01L27/118

    Abstract: A semiconductor integrated circuit is provided in which the transistor size can be minimized by only changing one mask after the performance of a prototype is tested. Impurity regions are formed in predetermined regions (formed of portions surrounded by solid lines and portions surrounded by broken lines) surrounded by a field insulating film on a semiconductor substrate for prototyping, and a prototype semiconductor integrated circuit is thereby manufactured, and then testing is performed. When the prototype semiconductor integrated circuit operates in a desired manner, impurity regions are formed in predetermined regions (formed of portions surrounded by solid lines only) surrounded by a field insulating film on a semiconductor substrate for shipment, and a semiconductor integrated circuit for shipment is thereby manufactured.

    Abstract translation: 提供了一种半导体集成电路，其中通过在测试原型的性能之后仅改变一个掩模，可以使晶体管尺寸最小化。 杂质区域形成在由用于原型的半导体衬底上的场绝缘膜包围的预定区域（由实线包围的部分和由虚线围绕的部分）之间，由此制造原型半导体集成电路，然后进行测试 。 当原型半导体集成电路以期望的方式工作时，杂质区域形成在由用于装运的半导体衬底上的场绝缘膜包围的预定区域（仅由实线包围的部分形成）中，并且用于装运的半导体集成电路 由此制造。

    Master-slice system semiconductor integrated circuit and design method thereof
    4.
    发明授权
    Master-slice system semiconductor integrated circuit and design method thereof 失效
    主切片系统半导体集成电路及其设计方法

    公开(公告)号：US06476425B1

    公开(公告)日：2002-11-05

    申请号：US09509307

    申请日：2000-06-22

    Applicant: Yoshiteru Ono

    Inventor： Yoshiteru Ono

    IPC: H01L27108

    CPC classification number: H01L27/11803 ,  H01L27/0207 ,  H01L27/11807 ,  Y10S257/909 ,  Y10S438/982

    Abstract: A placing and wiring method for a master slice type semiconductor integrated circuit is provided. The method is conducted by an automatic placing and routing apparatus with respect to a master slice 100 having a plurality of basic cells 110 formed in a matrix, in which first and second power source wirings 170 and 171 that traverse the plurality of basic cells 110 are connected to a plurality of signal wirings that are formed along a vertical direction to provide connections within each of the plurality of basic cells 110 and/or between the plurality of basic cells 110. The method includes: a first step of registering in the automatic pacing and routing apparatus definitions of effective pin positions A1-A14, B2-B13 and C1-C14; a second step of registering a net list in the automatic placing and routing apparatus; and a third step of determining the placement of pin positions and wiring routes, based on data for the definitions of the effective pin positions and the net list. The registered effective pin positions are provided on lattice grids 120, located inside and outside a region between the first and second power source wirings 170 and 171. In the circuit wired according to the definitions, contacts with respect to the drains are provided inside and outside the region between the first and second power source wirings 170 and 171, and the signal wirings do not cross the power source wirings.

    Abstract translation: 提供了一种用于主片式半导体集成电路的放置和布线方法。 该方法通过自动放置和路由装置对具有矩阵形成的多个基本单元110的主切片100进行，其中穿过多个基本单元110的第一和第二电源布线170和171是 连接到沿着垂直方向形成的多个信号布线，以提供多个基本单元110内和/或多个基本单元110之间的连接。该方法包括：第一步，在自动起搏 以及有效引脚位置A1-A14，B2-B13和C1-C14的路由设备定义; 在自动放置和路由设备中注册网络列表的第二步骤; 以及基于有效引脚位置和网络列表的定义的数据来确定引脚位置和布线路线的布置的第三步骤。 注册的有效销位置设置在位于第一和第二电源配线170和171之间的区域内外的格栅120上。在根据定义布线的电路中，相对于排水口的接触设置在内部和外部 第一和第二电源布线170和171之间的区域，并且信号布线不与电源布线交叉。

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