公开(公告)号：US20040041200A1

公开(公告)日：2004-03-04

申请号：US10360598

申请日：2003-02-06

Applicant: Hyundai Electronics America, Inc., a California corporation

Inventor： Sukyoon Yoon

IPC: H01L029/788

CPC classification number: H01L29/66825

Abstract: A flash memory device includes a substrate having first and second wells. The first well is defined within the second well. A plurality of trenches defines the substrate into a plurality of sub-columnar active regions. The trenches is formed within the first well and extends into the second well. A plurality of flash memory cells are formed on each of the sub-columnar active regions.

Abstract translation: 闪存器件包括具有第一和第二阱的衬底。 第一口井在第二口井内定义。 多个沟槽将衬底限定为多个子柱状有源区域。 沟槽形成在第一井内并且延伸到第二井中。 在每个子柱状活性区域上形成多个闪存单元。

公开(公告)号：US20040005738A1

公开(公告)日：2004-01-08

申请号：US10601351

申请日：2003-06-23

Applicant: Hyundai Electronics America

Inventor： Harold S. Crafts

IPC: H01L021/82

CPC classification number: H01L27/0207 ,  H01L27/11807 ,  H01L2924/0002 ,  Y10S257/909 ,  H01L2924/00

Abstract: The invention concerns integrated circuits in which a MACRO is embedded in a standard cell array. One level of metal is devoted exclusively to non-local interconnect, and a layer of polysilicon is devoted to local interconnect, thereby saving significant space.

公开(公告)号：US20020191613A1

公开(公告)日：2002-12-19

申请号：US10139603

申请日：2002-05-02

Applicant: Hyundai Electronics America

Inventor： Earle W. Jennings III

IPC: H04L012/56 ,  H04L012/28 ,  H04J003/22 ,  H04J003/16

CPC classification number: H04L29/06 ,  H04L49/351 ,  H04L49/352 ,  H04L69/18

Abstract: A multi-port packet processor on an integrated circuit provides an efficient means to interface multiple high-speed packet-based communications channels. The multi-port packet processor includes multiple port processors. Each port processor can include a channel interface for coupling to a respective communications channel, a channel processor for processing the data packets received through the channel interface, and an interprocessor communications interface for providing communication between the port processors. The channel interface can be designed to process data packets using a particular set of packet-based protocols. Alternatively, the channel interface can be designed having programmable controls to allow processing of data packets using a selected set, from a number of possible sets, of packet-based protocols.

公开(公告)号：US20010000306A1

公开(公告)日：2001-04-19

申请号：US09733427

申请日：2000-12-08

Applicant: Hyundai Electronics America, Inc.

Inventor： Sukyoon Yoon ,  Pavel Klinger ,  Joo Young Yoon

IPC: G11C016/06

CPC classification number: H01L27/11521 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C2211/565 ,  H01L27/115

Abstract: Instead of using a common substrate (101) for each sector of a flash memory, trenches are used to isolate columnar active substrate regions (304) of the substrate (101), and independent access to each of these columnar regions (304) is provided. First, the independent access to each of these columnar regions (304) provides a capability for achieving more precise control over the voltage on the floating gates (106). For example, flash memory in accordance with the present invention is better suited for multi-level storage (storing of more than 1 bit of information per cell). Second, the independent access to each of these columnar regions (304) also provides a capability for areas of flash memory smaller than an entire sector to be erased at one time. Finally, since both programming and erasing is achieved by way of cold electron tunneling from the columnar active substrate region (304), no high voltages need to be applied to either the drain (102) or source (104). This is advantageous in that the minimum distance required by cell punchthrough is reduced. Hence, higher densities of flash memory may be achieved.