公开(公告)号：US4800478A

公开(公告)日：1989-01-24

申请号：US932739

申请日：1986-10-31

Applicant: Isao Takahashi

Inventor： Isao Takahashi

IPC: H02M1/084 ,  H02M7/48 ,  H02P27/06 ,  H02M7/527 ,  H02P7/63

CPC classification number: H02M7/48 ,  H02M1/0845 ,  H02M7/53873 ,  H02M2007/53876

Abstract: In the control of a PWM inverter, there are various requirements such as decreasing a harmonic loss and acoustic noises, improving control response, optimizing switchings of the branches of the inverter in any condition, and simplification in circuit construction. In the present invention, the branches of the inverter are controlled in such that an evaluation function on the whole combination of the inverter and the load connected to the AC side of the inverter is made to be minimized.

Abstract translation: PCT No.PCT / JP85 / 00492 Sec。 371日期1986年10月31日第 102（e）1986年10月31日PCT PCT日期为1985年9月3日。在PWM逆变器的控制中，存在减少谐波损耗和声音噪声，改善控制响应，优化分支转换的各种要求 变频器在任何情况下，简化了电路结构。 在本发明中，逆变器的分支被控制成使逆变器的整体组合和连接到逆变器的AC侧的负载的评估功能最小化。

公开(公告)号：US4757436A

公开(公告)日：1988-07-12

申请号：US9478

申请日：1987-02-02

Applicant: Shigeta Ueda ,  Mitsuyuki Hombu ,  Takeki Ando ,  Kazuhiko Sasaki ,  Kazuo Honda ,  Hideaki Takahashi

Inventor： Shigeta Ueda ,  Mitsuyuki Hombu ,  Takeki Ando ,  Kazuhiko Sasaki ,  Kazuo Honda ,  Hideaki Takahashi

IPC: H02H7/125 ,  H02M1/084 ,  H02M7/12 ,  H02M7/155 ,  H02M7/162 ,  H02M7/48

CPC classification number: H02M1/0845 ,  H02H7/1252 ,  H02M7/1626

Abstract: In a current-type converter system in which a DC current is fed to a load through a pulsating current suppressing DC reactor from a current-type converter constituted by self-extinction elements connected in a bridge circuit, a converter protection apparatus is arranged such that when a fact that a terminal voltage of the DC reactor becomes an overvoltage is detected, the self-extinction elements are turned on so as to form a closed circuit including the DC reactor, the load, and the converter so that the overvoltage can be suppressed and continuous operation of the converter can be carried out.

Abstract translation: 在直流电流通过脉冲电流抑制DC电抗器从由连接在桥式电路中的自消除元件构成的电流型转换器馈送到负载的电流型转换器系统中，转换器保护装置被布置成使得 当检测到直流电抗器的端子电压变为过电压的事实时，自消除元件导通，形成包括直流电抗器，负载和转换器的闭合电路，从而能够抑制过电压 并且可以进行转换器的连续操作。

公开(公告)号：US4598353A

公开(公告)日：1986-07-01

申请号：US669143

申请日：1984-11-07

Applicant: John M. Leuthen

Inventor： John M. Leuthen

IPC: H02M1/084 ,  H02M7/162 ,  H02M7/08

CPC classification number: H02M7/1626 ,  H02M1/0845

Abstract: An SCR firing circuit allows the firing point to be changed. The firing circuit includes a ROM which has an output for each gate of each SCR. The ROM is programmed to fire the SCRs in a desired sequence. The ROM is driven by a counter, which counts pulses from an oscillator, the frequency of which is variable. The difference between the zero cross of the waveform and the ROM output is compared and averaged. The comparator output is summed with a variable DC demand voltage. The sum is applied to an integrator, which provides an integrated output to the oscillator to change the frequency of the oscillator if the firing point is changed.

Abstract translation: SCR点火电路允许改变点火点。 点火电路包括具有每个SCR的每个栅极的输出的ROM。 ROM被编程为以期望的顺序触发SCR。 ROM由计数器驱动，计数器来自振荡器的脉冲，其频率是可变的。 将波形的零交叉与ROM输出的差异进行比较和平均。 比较器输出与可变直流需求电压相加。 该和应用于积分器，该积分器为振荡器提供集成输出，以便在点火点改变时改变振荡器的频率。

公开(公告)号：US4565953A

公开(公告)日：1986-01-21

申请号：US626982

申请日：1984-07-02

Applicant: Paul M. Espelage ,  James M. Nowak

Inventor： Paul M. Espelage ,  James M. Nowak

IPC: H02J3/38 ,  H02M1/084 ,  H02M7/17 ,  H02M7/23 ,  H02M7/529 ,  H02P7/28 ,  H02P23/00 ,  H02P27/06 ,  H02P5/16

CPC classification number: H02P27/06 ,  H02M1/0845 ,  H02M7/529 ,  H02P23/0077 ,  Y10S388/903 ,  Y10S388/911 ,  Y10S388/912 ,  Y10S388/917

Abstract: A single microcomputer controls the firing time determination for two independent current regulators for two six pulse AC/DC converters which are part of a twelve pulse parallel controlled current inverter (CCI) AC motor drive. A very short high priority interrupt occurs when a motor channel source converter thyristor fires. This interrupt calls a longer, low priority current regulator interrupt informing it that a master channel source converter thyristor has just been fired. The current regulator causes a count to be loaded into a master fire counter and also loads a firing mask into a hardware latch or buffer. When the master fire counter times out the next thyristor pair of the master channel source converter is fired directly out of hardware. Similarly, there is a separate slave channel fire counter loaded after the current regulator is called by a short high priority interrupt when a thyristor in the slave channel source converter fires.

Abstract translation: 两个六脉冲AC / DC转换器的两个独立电流调节器的单个微机控制点火时间确定，它们是十二脉冲并联控制电流逆变器（CCI）交流电机驱动器的一部分。 当电机通道源转换器晶闸管触发时，会发生非常短的高优先级中断。 该中断调用较长的低优先级电流调节器中断，通知主通道源转换器晶闸管刚刚被触发。 电流调节器将计数加载到主火灾计数器中，并将启动掩码加载到硬件锁存器或缓冲器中。 当主火灾计数器超时时，主通道源转换器的下一个晶闸管对直接从硬件中发射。 类似地，当从属通道源转换器中的晶闸管发生触发时，在通过短暂的高优先级中断调用电流调节器之后，会有一个独立的从通道火灾计数器加载。

公开(公告)号：US4564819A

公开(公告)日：1986-01-14

申请号：US673340

申请日：1984-11-20

Applicant: Syunichi Hirose

Inventor： Syunichi Hirose

IPC: H02M7/155 ,  H02M1/08 ,  H02M1/084 ,  H02M7/12 ,  H02M7/162 ,  H03L7/06 ,  H02H7/125 ,  H02M7/04 ,  H03B27/00

CPC classification number: H02M7/1626 ,  H02M1/0845

Abstract: A phase detecting apparatus comprises a first PLL and a second PLL having a response time shorter than the response time of the first PLL. An AC voltage signal produced by the first PLL which is in phase with the detected AC voltage except until the expiration of the response time of the first PLL after an abrupt change in the phase of the detected AC voltage is normally applied to the second PLL. Until expiration of the response time of the first PLL after rising of the detected AC voltage to a certain level, the detected AC voltage is applied, in place of the AC voltage signal produced by the first PLL, to the second PLL. The second PLL provides a digital signal indicative of the phase of the detected AC voltage.

Abstract translation: 相位检测装置包括具有比第一PLL的响应时间短的响应时间的第一PLL和第二PLL。 由第一PLL产生的交流电压信号与除了检测到的交流电压的相位的突然变化之后的第一PLL的响应时间到期之前的检测到的交流电压相位相同，正常地施加到第二PLL。 直到检测到的AC电压升高到一定电平之后第一PLL的响应时间到期为止，将检测到的AC电压代替第一PLL产生的AC电压信号施加到第二PLL。 第二PLL提供指示检测到的AC电压的相位的数字信号。

公开(公告)号：US4468724A

公开(公告)日：1984-08-28

申请号：US365092

申请日：1982-04-02

Applicant: Tsutomu Omae ,  Toshihiko Matsuda ,  Makoto Tachikawa

Inventor： Tsutomu Omae ,  Toshihiko Matsuda ,  Makoto Tachikawa

IPC: H02M1/084 ,  H02M7/162 ,  H02M7/5387 ,  H02P7/292 ,  H02P23/00 ,  H02P13/26

CPC classification number: H02P23/0077 ,  H02M1/0845 ,  H02M7/1626 ,  H02M7/53873 ,  H02P7/293 ,  Y10S388/909

Abstract: A load DC motor is supplied with a DC current through a converter principally consisting of thyristors controlled by an ON-state control signal. The load current is detected both as to the mean value and the variation in time thereof. The mean value of the load current is calculated based on the load current values detected at the time of the present On-signal and the preceding ON-signal. The difference between the reference value and the mean value of the load current is calculated, and the difference between this differential signal and the variation of the load current is further calculated, so that the timing for providing the ON-signal is calculated based on the resultant differential signal.

Abstract translation: 负载直流电动机通过主要由由导通状态控制信号控制的晶闸管组成的转换器提供直流电流。 对平均值及其时间的变化检测负载电流。 负载电流的平均值根据当前接通信号和前一个ON信号时检测到的负载电流值进行计算。 计算基准值与负载电流的平均值之差，并进一步计算该差分信号与负载电流的变动量之间的差，从而基于 产生差分信号。

公开(公告)号：US4463415A

公开(公告)日：1984-07-31

申请号：US406310

申请日：1982-08-09

Applicant: Donald E. Vollrath

Inventor： Donald E. Vollrath

IPC: H02M1/084 ,  H02M7/155 ,  H02P13/24

CPC classification number: H02M1/0845 ,  H02M7/1557

Abstract: A timing generator for use with multi-phase controlled rectifier systems is disclosed in which a ramp signal is produced in phase synchronization with the power source and compared with the value of a command signal. The command signal is indicative of the desired SCR ignition angle. A sequencing circuit, having a finite number of output states is cyclically stepped from one state to the next by a comparator. The sequencing circuit couples a source of SCR-gating pulses to the appropriate SCR in accordance with its state and with a predetermined pattern of SCR ignitions which characterize the multi-phase source.One aspect of the invention provides the multiplexing of the comparator output whereby the command signal is offset by 60.degree. (electrical) after each comparator transition to set up conditions for the next transition.A further aspect of the invention provides for the generation of an alternate ramp, 180.degree. (electrical) out of phase with the foregoing ramp, and selectively applied to the comparator during periods in which the first ramp is discontinuous. The interrelationship of the 60.degree. interval associated with the command signal offset, and the 180.degree. relationship between the two ramps is advantageously utilized in the repeated offsetting of the command signal.

Abstract translation: 公开了一种与多相控制整流器系统一起使用的定时发生器，其中产生与电源相位同步的斜坡信号并与命令信号的值进行比较。 指令信号表示所需的SCR点火角。 具有有限数量的输出状态的排序电路由比较器从一个状态向下一个循环地步进。 排序电路根据其状态和特征为多相源的SCR点火的预定模式将SCR门控脉冲源耦合到适当的SCR。 本发明的一个方面提供了比较器输出的多路复用，由此在每个比较器转换之后，命令信号偏移60°（电），以设置下一个转换的条件。 本发明的另一方面提供了产生与上述斜坡180°（电）异相的交替斜坡，并且在第一斜坡不连续的时段期间选择性地施加到比较器。 与指令信号偏移相关联的60度间隔与两个斜坡之间的180°关系的相互关系有利地用于重复地偏移命令信号。

公开(公告)号：US4394723A

公开(公告)日：1983-07-19

申请号：US275075

申请日：1981-04-30

Applicant: John P. Hoffman

Inventor： John P. Hoffman

IPC: H02M1/084 ,  H02M7/162 ,  H02P13/24

CPC classification number: H02M1/0845 ,  H02M7/1623

Abstract: A power supply circuit (20) having an inductive load (12), three power lines (A,B,C) for conducting current of a 3-phase AC source, an SCR network (24) of six SCRs (1-6) for coupling the current of the source between the power lines (A,B,C) and the load (12), a phase sensor (30) for generating a reference signal in response to one reference phase voltage (AB) of the source, and a trigger circuit (35) for triggering "on" the SCRs (1-6) at predetermined phase angles relative to the voltage (AB). The power supply circuit (20) overcomes constraints such as load inductance which limit the rate of current build-up or decay through the load (12) by gating "on" the SCRs (1-6) at the predetermined phase angles to maximize such current build-up or decay.

Abstract translation: PCT No.PCT / US81 / 00578 Sec。 1981年4月30日 102（e）日期1981年4月30日PCT提交1981年4月30日PCT公布。 出版物WO82 / 03954 日期：1982年11月11日。一种电源电路（20），具有感应负载（12），三条电源线（A，B，C），用于传导三相交流电源的电流; SCR网络（24） 用于将电源线（A，B，C）和负载（12）之间的电流耦合的六个SCR（1-6），用于响应于一个参考相位电压产生参考信号的相位传感器（30） （AB），以及触发电路（35），用于相对于电压（AB）以预定的相位角度“触发”SCR（1-6）。 电源电路（20）克服了诸如负载电感之类的约束，其通过以预定相位角“选通”SCR（1-6）来限制电流积聚或衰减通过负载（12）的衰减，以使这样的最大化 当前的积聚或衰退。

公开(公告)号：US4327420A

公开(公告)日：1982-04-27

申请号：US164259

申请日：1980-06-30

Applicant: Michael Gdula ,  Raymond J. Hodsoll ,  Edwin C. Underkoffler

Inventor： Michael Gdula ,  Raymond J. Hodsoll ,  Edwin C. Underkoffler

IPC: G06F1/03 ,  H02M1/084 ,  H03B27/00 ,  G06F15/31 ,  H03B19/00

CPC classification number: H02M1/0845 ,  G06F1/0342

Abstract: A reference generator, providing a plurality of precisely-phased output signals, utilizes a microprocessor having a table of values for the output waveforms stored in a read-only memory thereof. The table entries include a multiplicity of values for providing a stepwise representation of each of the desired waveforms, which may have constant angular increments therebetween. The incremental tabular values are consecutively read responsive to the count in a timer, integral in the microcomputer, which is sequentially advanced by the pulse output of a voltage-to-frequency converter receiving a rate signal. The tabular values are converted to analog polyphase reference signals by a like number, equal to the number of phases, of digital-to-analog converters and associated low-pass filters. The output waveform peak amplitude is established by a dual-polarity reference voltage generator, responsive to a variable level signal. Essentially instantaneous reversal of the polyphase waveforms is provided by "angle complement" control of the present point utilized within the tables. The timer circuit provides steps of increasing size through the lookup-table to provide a gradual degradation in the number of steps in the output waveform when the rate signal exceeds the microcomputer execution speed upper limit.

Abstract translation: 提供多个精确定相输出信号的参考发生器利用存储在其只读存储器中的输出波形具有值表的微处理器。 表条目包括用于提供每个期望波形的逐步表示的多个值，其可以在它们之间具有恒定的角增量。 响应于微计算机中积分的定时器中的计数连续读取增量表格值，该计数器通过接收速率信号的电压 - 频率转换器的脉冲输出而顺序地提前。 表格值通过等于数模转换器和相关联的低通滤波器的相位数的相同数字转换为模拟多相参考信号。 输出波形峰值振幅由双极性参考电压发生器建立，响应于可变电平信号。 多相波形的基本瞬时反转由表内所使用的当前点的“角度补偿”控制提供。 定时器电路提供通过查找表增加尺寸的步骤，以便当速率信号超过微型计算机执行速度上限时提供输出波形中的步数的逐渐劣化。

公开(公告)号：US4195236A

公开(公告)日：1980-03-25

申请号：US889411

申请日：1978-03-23

Applicant: Anatoly Y. Kalinichenko ,  Viktor I. Kirillov ,  Aron A. Rabinovich ,  Vladimir V. Maleev ,  Vagiz S. Sakaev

Inventor： Anatoly Y. Kalinichenko ,  Viktor I. Kirillov ,  Aron A. Rabinovich ,  Vladimir V. Maleev ,  Vagiz S. Sakaev

IPC: H02M1/084 ,  H02M3/139 ,  H02P7/298 ,  H03K17/72

CPC classification number: H02M3/139 ,  H02M1/0845 ,  H02P7/298

Abstract: The proposed device comprises a master pulse generator and a control unit. The master pulse generator is connected to a clock pulse counter coupled to a thyristor-pulse converter. The control unit is connected to a bidirectional pulse counter. The proposed device also comprises a decoder whose inputs are connected to the clock pulse counter and to the bidirectional pulse counter; an individual AND gate whose input is connected to the clock pulse counter and whose output is connected to a second thyristor-pulse converter; and two groups of AND gates, each AND gate having an input connected to the decoder. The proposed device also has a NOT gate whose input is connected to the decoder; a sign flip-flop whose first output is connected to the AND gates of one of said groups and whose other output is connected to the first individual AND gate, to the AND gates of the other of said groups, and to the bidirectional pulse counter. Furthermore, the device is provided with a second individual AND gate whose inputs are connected to the NOT gate and to the bidirectional pulse counter and whose output is connected to the sign flip-flop; a third individual AND gate whose inputs are connected to the control unit and to the bidirectional pulse counter and whose output is connected to the sign flip-flop; and a fourth individual AND gate whose inputs are connected to the control unit, to the bidirectional pulse counter and whose output is connected to the sign flip-flop. The proposed device also includes a circuit for passing time-shifted trains of control pulses fed from the decoder to the thyristor-pulse converters.

Abstract translation: 所提出的装置包括主脉冲发生器和控制单元。 主脉冲发生器连接到与晶闸管脉冲转换器耦合的时钟脉冲计数器。 控制单元连接到双向脉冲计数器。 所提出的装置还包括其输入端连接到时钟脉冲计数器和双向脉冲计数器的解码器; 一个单独的与门，其输入连接到时钟脉冲计数器，其输出端连接到第二晶闸管脉冲转换器; 和两组与门，每个与门具有连接到解码器的输入。 所提出的装置还具有NOT门，其输入端连接到解码器; 一个符号触发器，其第一个输出连接到所述组中的一个的AND门并且其另一个输出连接到第一个别AND门，与另一个组的与门连接，并且连接到双向脉冲计数器。 此外，该装置设置有第二单独的与门，其输入连接到非门和双向脉冲计数器，并且其输出连接到符号触发器; 第三个独立的门，其输入连接到控制单元和双向脉冲计数器，并且其输出连接到符号触发器; 以及第四个单独的与门，其输入端连接到控制单元，连接到双向脉冲计数器，其输出端连接到符号触发器。 所提出的装置还包括用于将从解码器馈送到晶闸管脉冲转换器的控制脉冲的时移列车通过的电路。