公开(公告)号：US20230394316A1

公开(公告)日：2023-12-07

申请号：US18060582

申请日：2022-12-01

Applicant: WUHAN UNIVERSITY

Inventor： Yigang HE ,  Yingying ZHAO ,  Zhikai XING ,  Xiaoyu LIU ,  Xiao WANG

IPC: H02M3/139

CPC classification number: H02M3/139

Abstract: A DC/DC converter fault diagnosis method based on an improved sparrow search algorithm, includes: establishing an simulation module of the converter, selecting a leakage inductance current of a transformer as a diagnosis signal, and collecting diagnosis signal samples under OC faults of different power switching devices of the converter as a sample set; improving a global search ability of a sparrow search algorithm by using a Levy flight strategy; dividing the sample set into a training set and a test set, preliminarily establishing an architecture of a deep belief network, and initializing network parameters; optimizing a quantity of hidden-layer units of the deep belief network by using an improved sparrow search algorithm, to obtain a best quantity of hidden-layer units of the deep belief network; and training an optimized deep belief network obtained based on the improved sparrow search algorithm, and obtaining a fault diagnosis result based on a trained network.

公开(公告)号：US4204267A

公开(公告)日：1980-05-20

申请号：US895276

申请日：1978-04-10

Applicant: Anatoly Y. Kalinichenko

Inventor： Anatoly Y. Kalinichenko

IPC: H02M3/139 ,  H02P13/24

CPC classification number: H02M3/139

Abstract: The proposed digital control device controls a d.c. thyristor-pulse converter and comprises a decoder connected to a clock pulse counter and a reversible counter. The device further includes a control unit, a matching unit containing four AND gates and a sign flip-flop, and a switching unit having six AND gates and two flip-flops. A first AND gate of the switching unit is connected to a control electrode of a first thyristor, a second AND gate of the switching unit is connected to a control electrode of a second thyristor, a third AND gate is connected to a control electrode of a third thyristor, a fourth AND gate is connected to control electrode of a fourth thyristor, a fifth AND gate is connected to the control electrodes of the first and third thyristors, and a sixth AND gate is connected to the control electrodes of the second and fourth thyristors. The clock pulse counter and the AND gates are connected to the flip-flops of the switching unit. In the matching unit, the first and second AND gates are connected to a position selection output of the control unit and the third and fourth AND gates are connected to a position return output of the control unit. Outputs of the second and fourth AND gates are connected to an add input of the reversible counter and the subtract input is connected to outputs of the first and third AND gates of the matching unit. The reversible counter is connected to the decoder, which is connected to the sign flip-flop. A second input of the sign flip-flop is connected to the decoder and to a reset output of the control unit. The sign flip-flop is connected to the second and third AND gates of the matching unit and the first, second, third and fourth AND gates of the switching unit. Another output of the sign flip-flop is connected to the first and fourth AND gates of the matching unit and the fifth and sixth AND gates of the switching unit.

Abstract translation: 所提出的数字控制装置控制直流 晶闸管脉冲转换器，并且包括连接到时钟脉冲计数器和可逆计数器的解码器。 该装置还包括控制单元，包含四个与门和符号触发器的匹配单元，以及具有六个与门和两个触发器的开关单元。 开关单元的第一AND门连接到第一晶闸管的控制电极，开关单元的第二与门连接到第二晶闸管的控制电极，第三与门连接到第一晶闸管的控制电极 第三晶闸管，第四AND门连接到第四晶闸管的控制电极，第五AND门连接到第一和第三晶闸管的控制电极，第六与门连接到第二和第四晶闸管的控制电极 晶闸管 时钟脉冲计数器和与门连接到开关单元的触发器。 在匹配单元中，第一和第二与门连接到控制单元的位置选择输出，第三和第四与门连接到控制单元的位置返回输出。 第二和第四与门的输出连接到可逆计数器的加法输入，减法输入连接到匹配单元的第一和第三与门的输出。 可逆计数器连接到解码器，该解码器连接到符号触发器。 符号触发器的第二输入连接到解码器和控制单元的复位输出。 符号触发器连接到匹配单元的第二和第三与门以及开关单元的第一，第二，第三和第四AND门。 符号触发器的另一个输出连接到开关单元的匹配单元的第一和第四与门以及第五和第六与门。

公开(公告)号：US4195236A

公开(公告)日：1980-03-25

申请号：US889411

申请日：1978-03-23

Applicant: Anatoly Y. Kalinichenko ,  Viktor I. Kirillov ,  Aron A. Rabinovich ,  Vladimir V. Maleev ,  Vagiz S. Sakaev

Inventor： Anatoly Y. Kalinichenko ,  Viktor I. Kirillov ,  Aron A. Rabinovich ,  Vladimir V. Maleev ,  Vagiz S. Sakaev

IPC: H02M1/084 ,  H02M3/139 ,  H02P7/298 ,  H03K17/72

CPC classification number: H02M3/139 ,  H02M1/0845 ,  H02P7/298

Abstract: The proposed device comprises a master pulse generator and a control unit. The master pulse generator is connected to a clock pulse counter coupled to a thyristor-pulse converter. The control unit is connected to a bidirectional pulse counter. The proposed device also comprises a decoder whose inputs are connected to the clock pulse counter and to the bidirectional pulse counter; an individual AND gate whose input is connected to the clock pulse counter and whose output is connected to a second thyristor-pulse converter; and two groups of AND gates, each AND gate having an input connected to the decoder. The proposed device also has a NOT gate whose input is connected to the decoder; a sign flip-flop whose first output is connected to the AND gates of one of said groups and whose other output is connected to the first individual AND gate, to the AND gates of the other of said groups, and to the bidirectional pulse counter. Furthermore, the device is provided with a second individual AND gate whose inputs are connected to the NOT gate and to the bidirectional pulse counter and whose output is connected to the sign flip-flop; a third individual AND gate whose inputs are connected to the control unit and to the bidirectional pulse counter and whose output is connected to the sign flip-flop; and a fourth individual AND gate whose inputs are connected to the control unit, to the bidirectional pulse counter and whose output is connected to the sign flip-flop. The proposed device also includes a circuit for passing time-shifted trains of control pulses fed from the decoder to the thyristor-pulse converters.

Abstract translation: 所提出的装置包括主脉冲发生器和控制单元。 主脉冲发生器连接到与晶闸管脉冲转换器耦合的时钟脉冲计数器。 控制单元连接到双向脉冲计数器。 所提出的装置还包括其输入端连接到时钟脉冲计数器和双向脉冲计数器的解码器; 一个单独的与门，其输入连接到时钟脉冲计数器，其输出端连接到第二晶闸管脉冲转换器; 和两组与门，每个与门具有连接到解码器的输入。 所提出的装置还具有NOT门，其输入端连接到解码器; 一个符号触发器，其第一个输出连接到所述组中的一个的AND门并且其另一个输出连接到第一个别AND门，与另一个组的与门连接，并且连接到双向脉冲计数器。 此外，该装置设置有第二单独的与门，其输入连接到非门和双向脉冲计数器，并且其输出连接到符号触发器; 第三个独立的门，其输入连接到控制单元和双向脉冲计数器，并且其输出连接到符号触发器; 以及第四个单独的与门，其输入端连接到控制单元，连接到双向脉冲计数器，其输出端连接到符号触发器。 所提出的装置还包括用于将从解码器馈送到晶闸管脉冲转换器的控制脉冲的时移列车通过的电路。

公开(公告)号：US20180226900A1

公开(公告)日：2018-08-09

申请号：US15579935

申请日：2016-07-13

Applicant: NR ELECTRIC CO., LTD ,  NR ENGINEERING CO., LTD

Inventor： Yeyuan XIE ,  Dongming CAO ,  Tiangui JIANG ,  Minglian ZHU ,  Guanxian YIN

IPC: H02M7/5387 ,  H02M1/32

CPC classification number: H02M7/5387 ,  G06F13/00 ,  H01M10/4257 ,  H02J7/0021 ,  H02M1/32 ,  H02M3/00 ,  H02M3/137 ,  H02M3/139 ,  H02M7/00 ,  H02M7/219 ,  H02M2001/325 ,  H02M2001/327 ,  H02M2007/4835

Abstract: Disclosed are a modulation method of a modular multilevel converter and a fault isolation method of a submodule unit. The modulation method comprises a first mode and a second mode, and the first mode and the second mode operate cyclically. In the first mode, a first power semiconductor switch and a second power semiconductor switch are turned on alternately, while a third power semiconductor switch is turned off normally and a fourth power semiconductor switch is turned on normally. In the second mode, the third power semiconductor switch and the fourth power semiconductor switch are turned on alternately, while the first power semiconductor switch is turned on normally and the second power semiconductor switch is turned off normally. The method enables junction temperatures of the power semiconductor switches used to be equalized, increases an operation safety margin of the converter, effectively increase the capacity of the converter without increasing engineering costs, and achieve better performance in both economic efficiency and technicality.

公开(公告)号：US20140049232A1

公开(公告)日：2014-02-20

申请号：US13937943

申请日：2013-07-09

Applicant: Gang Chen ,  Chunbo Liu ,  Gabor Reizik

Inventor： Gang Chen ,  Chunbo Liu ,  Gabor Reizik

IPC: G05F1/10

CPC classification number: G05F1/10 ,  H02M1/143 ,  H02M1/15 ,  H02M3/139 ,  H02M3/156 ,  H02M3/157

Abstract: In one embodiment, a method of forming a ripple suppressor circuit includes a configuring the ripple suppressor circuit to receive a first signal that is representative of a requested voltage and a second signal that is a filtered value of the first signal. The method also includes configuring the ripple suppressor circuit to determine a peak value of the second signal responsively to the first signal and to determine a minimum value of the second signal responsively to the first signal. The method may also include configuring the ripple suppressor circuit to form an average value of the peak value and the minimum value.

Abstract translation: 在一个实施例中，形成纹波抑制电路的方法包括配置纹波抑制电路以接收代表请求电压的第一信号和作为第一信号的滤波值的第二信号。 该方法还包括配置纹波抑制电路以响应于第一信号确定第二信号的峰值，并响应于第一信号确定第二信号的最小值。 该方法还可以包括配置纹波抑制电路以形成峰值和最小值的平均值。

公开(公告)号：US4207516A

公开(公告)日：1980-06-10

申请号：US937568

申请日：1978-08-28

Applicant: William E. Babcock

Inventor： William E. Babcock

IPC: H02M3/139 ,  G05F1/56

CPC classification number: H02M3/139 ,  Y10S323/908

Abstract: A switching regulator for regulating an input voltage having an alternating current component. Closure of the regulator switch is determined by a phase shifted switching signal obtained from a control network. In normal operation a varying bias signal coupled to the control circuit varies the phase shift of the switching signal to vary the instant of regulator switch closure. During startup, a capacitance coupled to the control circuit and to the input voltage provides an additional bias signal to delay the switching signal to prevent regulator switch closure during the peak magnitude of the alternating current input voltage component to thereby limit the peak inrush current in the regulator circuit.

Abstract translation: 一种用于调节具有交流分量的输入电压的开关调节器。 调节器开关的闭合由从控制网络获得的相移开关信号确定。 在正常操作中，耦合到控制电路的变化的偏置信号改变开关信号的相移以改变调节器开关闭合的时刻。 在启动期间，耦合到控制电路和输入电压的电容提供附加的偏置信号以延迟开关信号，以防止在交流电输入电压分量的峰值幅度期间调节器开关闭合，从而限制交流输入电压分量中的峰值浪涌电流 调节电路。

公开(公告)号：US4200908A

公开(公告)日：1980-04-29

申请号：US892790

申请日：1978-04-03

Applicant: Anatoly Y. Kalinichenko ,  Valentin M. Vlasov ,  Grigory E. Kiksman

Inventor： Anatoly Y. Kalinichenko ,  Valentin M. Vlasov ,  Grigory E. Kiksman

IPC: H02M1/084 ,  H02M3/139 ,  H02M7/515

CPC classification number: H02M1/0845 ,  H02M3/139

Abstract: A device for digital control of a polyphase thyristor-pulse converter comprises a master oscillator connected to a clock pulse counter. The clock pulse counter is connected to the power thyristors of the thyristor-pulse converter through a decoder for time-constant pulse trains. The device also comprises a control unit connected to a bidirectional pulse counter. Furthermore, the device comprises decoders for time-shifted pulse trains, each decoder having inputs connected to the logical outputs of the clock pulse counter and having outputs connected to the other power thyristors of the thyristor-pulse converter.

Abstract translation: 用于多相晶闸管脉冲转换器的数字控制的装置包括连接到时钟脉冲计数器的主振荡器。 时钟脉冲计数器通过用于时间恒定脉冲串的解码器连接到晶闸管脉冲转换器的功率晶闸管。 该装置还包括连接到双向脉冲计数器的控制单元。 此外，该装置包括用于时移脉冲串的解码器，每个解码器具有连接到时钟脉冲计数器的逻辑输出的输入，并具有连接到晶闸管 - 脉冲转换器的其他功率晶闸管的输出。

公开(公告)号：US09893613B1

公开(公告)日：2018-02-13

申请号：US15637593

申请日：2017-06-29

Applicant: Mitsubishi Electric Corporation

Inventor： Mai Nakada ,  Ryota Kondo ,  Matahiko Ikeda ,  Yuya Tanaka ,  Shingo Kato

IPC: H02M3/158 ,  H02M3/142 ,  H02M3/07 ,  H02M3/139 ,  H02M3/18

CPC classification number: H02M3/142 ,  H02M3/07 ,  H02M3/139 ,  H02M3/158 ,  H02M3/1582 ,  H02M3/18 ,  H02M2003/1586

Abstract: To provide a DC/DC converter which does not need to switch a change direction of a control value depending on a power transmission direction between low voltage side and high voltage side, and can control a voltage of a charge and discharge capacitor. A DC/DC converter which controls voltage of a charge and discharge capacitor by a controller that performs a Δduty control which changes an ON duty ratio difference of semiconductor circuits, and a phase shift control which changes a phase difference of an ON period of semiconductor circuits.

公开(公告)号：US4433370A

公开(公告)日：1984-02-21

申请号：US362274

申请日：1982-03-26

Applicant: Sam M. Karadsheh ,  Thomas A. Radomski

Inventor： Sam M. Karadsheh ,  Thomas A. Radomski

IPC: H02M3/139 ,  H02M3/142 ,  H02P7/29 ,  H02M3/315 ,  H02H7/122 ,  H02P7/28

CPC classification number: H02M3/142 ,  H02M3/139 ,  H02P7/2913 ,  Y10S388/915 ,  Y10S388/92

Abstract: The current in each phase of a multiple phase chopper is sensed and compared to a reference overcurrent value. Any chopper phase reaching overcurrent and any chopper phase on for a longer period of time are turned off immediately. The conduction periods of chopper phases that have been on for a shorter period of time than the overcurrent phase are similarly shortened to maintain balanced phase conduction and minimize the ripple content of the source current. The phase relationship among the various chopper phases is adjusted in response to an overcurrent turn-off to allow the commutation network associated with such phase to be adequately charged before the generation of a current turn-on for another phase.

Abstract translation: 检测多相斩波器的每相中的电流并将其与参考过电流值进行比较。 任何斩波相达到过电流和任何斩波相位较长时间都将立即关闭。 相对于过电流相位较短时间段的斩波相的导通时间同样缩短，以保持平衡相导通，并使源极电流的波动含量最小化。 响应于过电流关断来调整各个斩波相之间的相位关系，以便在产生用于另一相的电流接通之前允许与这种相位相关联的换向网络被充分地充电。

公开(公告)号：US4215393A

公开(公告)日：1980-07-29

申请号：US939339

申请日：1978-09-05

Applicant: Anatoly Y. Kalinichenko

Inventor： Anatoly Y. Kalinichenko

IPC: H02M3/139 ,  H02M7/515

CPC classification number: H02M3/139

Abstract: An apparatus for numerical control of a thyristor inverter comprises a decoder connected to a clock counter and a bidirectional counter, a control unit and a switching unit having seven AND gates, a NOT gate, a sign flip-flop, and a delay circuit. The clock counter is coupled to the first inputs of the first and second AND gates, the output of the first AND gate is coupled to the gate electrodes of the main and recharging thyristors of the thyristor inverter, and the outputs of the second and third gates are AND coupled to the gate electrode of the dropping thyristor. The first output of the decoder is coupled to the first inputs of the third and fourth AND gates, the output of an additional AND gate being coupled to the gate electrode of an additional thyristor and, via the delay circuit, to the gate electrode of the recharging thyristor. The control unit is coupled to the first inputs of the fifth, sixth and seventh AND gates. The second output of the decoder is coupled to the second input of the seventh AND gate and, via the NOT gate, to the second input of the sixth AND gate; and the second input of the fifth AND gate is coupled to the third output of the decoder. The outputs of the fifth, sixth and seventh and gates are coupled to the inputs of the sign flip-flop. The outputs of the sign flip-flop are respectively coupled to the second inputs of the second and fourth and first and third AND gates.

Abstract translation: 晶闸管逆变器的数值控制装置包括连接到时钟计数器和双向计数器的解码器，具有七个与门的控制单元和开关单元，非门，符号触发器和延迟电路。 时钟计数器耦合到第一和第二与门的第一输入，第一与门的输出耦合到晶闸管反相器的主充电晶闸管和栅极电极，第二和第三栅极的输出端 AND与耦合到滴水晶闸管的栅电极。 解码器的第一输出耦合到第三和第四与门的第一输入，附加的与门的输出耦合到附加晶闸管的栅电极，并且经由延迟电路耦合到栅极电极 充电晶闸管。 控制单元耦合到第五，第六和第七AND门的第一输入端。 解码器的第二输出端耦合到第七与门的第二输入端，并且经由非门，耦合到第六与门的第二输入; 并且第五与门的第二输入端耦合到解码器的第三输出端。 第五，第六和第七和第七和第五输出端与输入的符号触发器耦合。 符号触发器的输出分别耦合到第二和第四以及第一和第三与门的第二输入端。