公开(公告)号：US20180209035A1

公开(公告)日：2018-07-26

申请号：US15857384

申请日：2017-12-28

Applicant: Applied Materials, Inc.

Inventor： Jingjing LIU ,  Ludovic GODET ,  Srinivas D. NEMANI ,  Yongmei CHEN ,  Anantha K. SUBRAMANI

IPC: C23C14/34 ,  H01L21/265 ,  H01J37/34 ,  H01J37/32 ,  C23C14/50 ,  C23C14/35 ,  C23C14/48

Abstract: Embodiments of the present disclosure provide a sputtering chamber with in-situ ion implantation capability. In one embodiment, the sputtering chamber comprises a target, an RF and a DC power supplies coupled to the target, a support body comprising a flat substrate receiving surface, a bias power source coupled to the support body, a pulse controller coupled to the bias power source, wherein the pulse controller applies a pulse control signal to the bias power source such that the bias power is delivered either in a regular pulsed mode having a pulse duration of about 100-200 microseconds and a pulse repetition frequency of about 1-200 Hz, or a high frequency pulsed mode having a pulse duration of about 100-300 microseconds and a pulse repetition frequency of about 200 Hz to about 20 KHz, and an exhaust assembly having a concentric pumping port formed through a bottom of the processing chamber.

公开(公告)号：US20180171476A1

公开(公告)日：2018-06-21

申请号：US15449891

申请日：2017-03-03

Applicant: Applied Materials, Inc.

Inventor： Ludovic GODET ,  Christine Y. OUYANG

IPC: C23C16/455 ,  C23C16/56 ,  C23C16/48 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L21/67

CPC classification number: H01L21/67167 ,  C23C16/04 ,  C23C16/047 ,  C23C16/45525 ,  C23C16/483 ,  C23C16/56 ,  H01L21/02057 ,  H01L21/3105 ,  H01L21/311

Abstract: Implementations described herein relate to selective removal processes. More specifically, laser thermal processing is utilized to selectively remove a self-assembled monolayer (SAM) material from a portion of a substrate. In one example, laser thermal processing may be utilized to selectively remove SAM materials from a metallic material layer preferentially to a dielectric material layer. Other implementations provide for a substrate process apparatus which includes a pre-clean chamber, a SAM deposition chamber, a laser thermal process chamber, an atomic layer deposition (ALD) chamber, and a post-process chamber all disposed about a central process chamber.

公开(公告)号：US20180052396A1

公开(公告)日：2018-02-22

申请号：US15782425

申请日：2017-10-12

Applicant: Applied Materials, Inc.

Inventor： Peng XIE ,  Ludovic GODET ,  Christopher BENCHER

IPC: G03F7/38 ,  G03F7/26 ,  G03F7/004

CPC classification number: G03F7/38 ,  G03F7/0045 ,  G03F7/26

Abstract: Methods and apparatuses for minimizing line edge/width roughness in lines formed by photolithography are provided. The random diffusion of acid generated by a photoacid generator during a lithography process contributes to line edge/width roughness. Methods disclosed herein apply an electric field, a magnetic field, and/or a standing wave during photolithography processes. The field and/or standing wave application controls the diffusion of the acids generated by the photoacid generator along the line and spacing direction, preventing the line edge/width roughness that results from random diffusion. Apparatuses for carrying out the aforementioned methods are also disclosed herein.

公开(公告)号：US20170287752A1

公开(公告)日：2017-10-05

申请号：US15445303

申请日：2017-02-28

Applicant: Applied Materials, Inc.

Inventor： Ludovic GODET ,  Mehdi VAEZ-IRAVANI ,  Todd EGAN ,  Mangesh BANGAR ,  Concetta RICCOBENE ,  Abdul Aziz KHAJA ,  Srinivas D. NEMANI ,  Ellie Y. YIEH ,  Sean S. KANG

IPC: H01L21/67 ,  H01L21/265 ,  H01L21/66

CPC classification number: H01L21/67259 ,  H01L21/265 ,  H01L21/67167 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/67207 ,  H01L21/67213 ,  H01L21/67288 ,  H01L22/20

Abstract: Embodiments of the disclosure provide an integrated system for performing a measurement process and a lithographic overlay error correction process on a semiconductor substrate in a single processing system. In one embodiment, a processing system includes at least a load lock chamber, a transfer chamber coupled to the load lock chamber, an ion implantation processing chamber coupled to or in the transfer chamber, and a metrology tool coupled to the transfer chamber, wherein the metrology tool is adapted to obtain stress profile or an overlay error on a substrate disposed in the metrology tool.

公开(公告)号：US20170221701A1

公开(公告)日：2017-08-03

申请号：US15422116

申请日：2017-02-01

Applicant: Applied Materials, Inc.

Inventor： Aaron Muir HUNTER ,  Kong Lung Samuel CHAN ,  Christine Y. OUYANG ,  Ludovic GODET

IPC: H01L21/027 ,  H01L21/687 ,  H01L21/67 ,  H01L21/3105 ,  H01L21/324

CPC classification number: H01L21/0271 ,  G03F7/0002 ,  H01L21/31058 ,  H01L21/324 ,  H01L21/67115 ,  H01L21/68764

Abstract: A semiconductor processing method and semiconductor device are described. A substrate having a directed self-assembling material disposed thereon is heated to a temperature above the glass transition temperature of the directed self-assembling material, for example from about 325° C. to 380° C., in an RTP process. The substrate is then cooled at a controlled rate of less than 5° C./sec to 100° C. or lower.

公开(公告)号：US20170200587A1

公开(公告)日：2017-07-13

申请号：US15399084

申请日：2017-01-05

Applicant: Applied Materials, Inc.

Inventor： Ludovic GODET ,  Jun XUE ,  Sang Ki NAM

IPC: H01J37/32 ,  H01L21/3065

CPC classification number: H01J37/32082 ,  H01J37/32357 ,  H01J37/32422 ,  H01J37/3244 ,  H01J37/32449 ,  H01J37/32532 ,  H01J37/32559 ,  H01J37/32568 ,  H01J2237/334 ,  H01L21/3065

Abstract: Implementations described herein relate to apparatus and methods for performing atomic layer etching (ALE). Pulsed plasma generation and subsequent bias application to plasma afterglow may provide for improved ALE characteristics. Apparatus described herein provide for plasma generation from one or more plasma sources and biasing of plasma afterglow to facilitate material removal from a substrate.

公开(公告)号：US20170154776A1

公开(公告)日：2017-06-01

申请号：US15432368

申请日：2017-02-14

Applicant: Applied Materials, Inc.

Inventor： Ludovic GODET ,  Srinivas D. NEMANI ,  Erica CHEN ,  Jun XUE ,  Ellie Y. YIEH ,  Gary E. DICKERSON

IPC: H01L21/033 ,  H01L21/3105

CPC classification number: H01L21/0337 ,  H01J2237/24528 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31155 ,  H01L21/32 ,  H01L21/76205 ,  H01L21/7624 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7831

Abstract: Embodiments of the present disclosure relate to precision material modification of three dimensional (3D) features or advanced processing techniques. Directional ion implantation methods are utilized to selectively modify desired regions of a material layer to improve etch characteristics of the modified material. For example, a modified region of a material layer may exhibit improved etch selectivity relative to an unmodified region of the material layer. Methods described herein are useful for manufacturing 3D hardmasks which may be advantageously utilized in various integration schemes, such as fin isolation and gate-all-around, among others. Multiple directional ion implantation processes may also be utilized to form dopant gradient profiles within a modified layer to further influence etching processes.

公开(公告)号：US20170053797A1

公开(公告)日：2017-02-23

申请号：US15346306

申请日：2016-11-08

Applicant: Applied Materials, Inc.

Inventor： Srinivas D. NEMANI ,  Ellie Y. YIEH ,  Ludovic GODET ,  Yin FAN

IPC: H01L21/02 ,  H01L29/66 ,  H01J37/32 ,  H01L21/3115

CPC classification number: H01L21/02304 ,  H01J37/32357 ,  H01J37/32403 ,  H01J37/32422 ,  H01L21/0228 ,  H01L21/02321 ,  H01L21/0234 ,  H01L21/31155 ,  H01L29/66795 ,  H01L29/66803

Abstract: Methods for forming fin structure with desired materials formed on different locations of the fin structure using a selective deposition process for three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips are provided. In one embodiment, a method of forming a structure with desired materials on a substrate includes forming a patterned self-assembled monolayer on a circumference of a structure formed on a substrate, wherein the patterned self-assembled monolayer includes a treated layer formed among a self-assembled monolayer, and performing an atomic layer deposition process to form a material layer predominantly on the self-assembled monolayer from the patterned self-assembled monolayer.

Abstract translation: 提供了使用用于半导体芯片的鳍式场效应晶体管（FinFET）的三维（3D）堆叠的选择性沉积工艺在翅片结构的不同位置形成所需材料的翅片结构的方法。 在一个实施方案中，在衬底上形成具有期望材料的结构的方法包括在形成在衬底上的结构的圆周上形成图案化的自组装单层，其中所述图案化的自组装单层包括在自身中形成的处理层 并且执行原子层沉积工艺，以从图案化的自组装单层形成主要在自组装单层上的材料层。

公开(公告)号：US20160194758A1

公开(公告)日：2016-07-07

申请号：US14635589

申请日：2015-03-02

Applicant: Applied Materials, Inc.

Inventor： Srinivas D. NEMANI ,  Erica CHEN ,  Ludovic GODET ,  Jun XUE ,  Ellie Y. YIEH

IPC: C23C16/56 ,  C23C16/32 ,  C23C14/48 ,  C23C16/36 ,  C23C16/40 ,  C23C16/30 ,  C23C16/34

CPC classification number: C23C16/56 ,  C23C16/045 ,  C23C16/401

Abstract: Embodiments described herein relate to methods for forming flowable chemical vapor deposition (FCVD) films suitable for high aspect ratio gap fill applications. Various process flows described include ion implantation processes utilized to treat a deposited FCVD film to improve dielectric film density and material composition. Ion implantation processes, curing processes, and annealing processes may be utilized in various sequence combinations to form dielectric films having improved densities at temperatures within the thermal budget of device materials. Improved film quality characteristics include reduced film stress and reduced film shrinkage when compared to conventional FCVD film formation processes.

Abstract translation: 本文所述的实施方案涉及用于形成适用于高纵横比间隙填充应用的可流动化学气相沉积（FCVD）膜的方法。 所描述的各种工艺流程包括用于处理沉积的FCVD膜以改善电介质膜密度和材料组成的离子注入工艺。 离子注入工艺，固化过程和退火工艺可以以各种顺序组合使用，以在器件材料的热预算内的温度下形成具有改善的密度的电介质膜。 与常规的FCVD成膜方法相比，改进的膜质量特性包括膜应力减小和膜收缩减小。

公开(公告)号：US20160064500A1

公开(公告)日：2016-03-03

申请号：US14833858

申请日：2015-08-24

Applicant: Applied Materials, Inc.

Inventor： Yongmei CHEN ,  Christopher S. NGAI ,  Jingjing LIU ,  Chentsau YING ,  Ludovic GODET

IPC: H01L29/423 ,  H01L21/311 ,  H01L29/51 ,  H01L21/02 ,  H01L29/49 ,  H01L27/115

CPC classification number: H01L21/0332 ,  C23C16/26 ,  C23C16/27 ,  C23C16/274 ,  C23C16/279 ,  H01L21/02115 ,  H01L21/02274 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/31111 ,  H01L21/31122 ,  H01L21/31144 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/49 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/518

Abstract: A nanocrystalline diamond layer for use in forming a semiconductor device and methods for using the same are disclosed herein. The device can include a substrate with a processing surface and a supporting surface, a device layer formed on the processing surface and a nanocrystalline diamond layer formed on the processing layer, the nanocrystalline diamond layer having an average grain size of between 2 nm and 5 nm. The method can include positioning a substrate in a process chamber, depositing a device layer on a processing surface, depositing a nanocrystalline diamond layer on the device layer, the nanocrystalline diamond layer having an average grain size of between 2 nm and 5 nm, patterning and etching the nanocrystalline diamond layer, etching the device layer to form a feature and ashing the nanocrystalline diamond layer from the surface of the device layer.

Abstract translation: 本文公开了用于形成半导体器件的纳米晶体金刚石层及其使用方法。 该器件可以包括具有处理表面和支撑表面的衬底，形成在处理表面上的器件层和形成在处理层上的纳米晶体金刚石层，该纳米晶体金刚石层的平均晶粒尺寸在2nm和5nm之间 。 该方法可以包括将衬底定位在处理室中，在处理表面上沉积器件层，在器件层上沉积纳米晶体金刚石层，平均晶粒尺寸在2nm和5nm之间的纳米晶体金刚石层，图案化和 蚀刻纳米晶体金刚石层，蚀刻器件层以形成特征并从器件层的表面灰化纳米晶体金刚石层。