公开(公告)号：US10199504B2

公开(公告)日：2019-02-05

申请号：US14905251

申请日：2015-08-05

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zhengliang Li ,  Qi Yao ,  Zhanfeng Cao ,  Bin Zhang ,  Xiaolong He ,  Jincheng Gao ,  Xiangchun Kong ,  Wei Zhang

IPC: H01L29/10 ,  H01L29/786 ,  H01L21/28 ,  H01L27/12 ,  H01L29/45 ,  H01L29/49

Abstract: Embodiments of the present invention disclose a thin film transistor and a manufacturing method thereof, an array substrate, and a display device, which relates to the field of display technology, and solves the problem that the adhesion of the electrode thin film with the adjacent thin film layer in the thin film transistor of the prior art is relatively bad. More specifically, an embodiment of the present invention provides a thin film transistor, comprising a gate, a source, a drain and a buffer layer, the buffer layer is located at one side or two sides of the gate, the source or the drain, the material of the buffer layer is a copper alloy material, the copper alloy material contains nitrogen element or oxygen element, the copper alloy material further contains aluminum element.

公开(公告)号：US10192893B2

公开(公告)日：2019-01-29

申请号：US14895352

申请日：2015-05-15

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zhanfeng Cao ,  Feng Zhang ,  Qi Yao ,  Jincheng Gao ,  Bin Zhang ,  Xiaolong He ,  Zhengliang Li ,  Wei Zhang

IPC: H01L27/12 ,  G02F1/1362 ,  G02F1/1345

Abstract: An array substrate and a display device are provided. The array substrate comprises a plurality of signal lines (40), a plurality of connecting lines (50) and a driving module (60) in a peripheral region (1) outside a display region (2); the connecting lines (50) are configured for connecting the signal lines (40) and the driving module (60), to transmit signal from the signal lines (40) to the driving module (60), wherein, at least one of the connecting lines (50) and at least one of the signal lines (40) are designed to intersect with and insulated from each other in a first region (N). The at least one of the signal lines (40) includes, in a second region (0) other than the first region (N), a first electrode line layer (401) and a second electrode line layer (402), while, in the first region (N), includes the first electrode line layer (401) but does not include the second electrode line layer (402). The array substrate may prevent problems of electrostatic accumulation or short circuit from occurring between the connecting lines (50) and the second electrode line layer (402).

公开(公告)号：US10181482B2

公开(公告)日：2019-01-15

申请号：US15306550

申请日：2016-02-24

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zhengliang Li ,  Qi Yao ,  Bin Zhang ,  Zhanfeng Cao ,  Wei Zhang ,  Xuefei Sun ,  Bin Zhou ,  Jincheng Gao

IPC: H01L29/12 ,  H01L27/12 ,  H01L21/027 ,  H01L29/786

Abstract: According to an embodiment of the present disclosure, a method for manufacturing the array substrate includes forming a first transparent conductive layer and a metallic layer successively on a base substrate, and forming a gate electrode, a source electrode, a drain electrode and a first transparent electrode by one patterning process.

公开(公告)号：US10126544B2

公开(公告)日：2018-11-13

申请号：US15525445

申请日：2016-07-22

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiaolong He ,  Zhanfeng Cao ,  Qi Yao ,  Bin Zhang ,  Zhengliang Li ,  Wei Zhang ,  Tingting Zhou ,  Jincheng Gao ,  Jiushi Wang

IPC: G02B26/00

Abstract: A display panel includes a first substrate and a second substrate which are arranged opposed to each other. The space between the first substrate and the second substrate is separated into a plurality of sub-pixel regions. Within each sub pixel region, a first electrode, a first fluid layer, a second fluid layer, a hydrophobic dielectric layer and a second electrode are arranged in this order. The first fluid layer is made of hydrophilic liquid. The second fluid layer is made of ink. When no electric field is applied between the first electrode and the second electrode, the ink spreads over the surface of the hydrophobic dielectric layer. When an electric field is applied between the first electrode and the second electrode, the ink aggregates to expose the hydrophobic dielectric layer.

公开(公告)号：US10049634B2

公开(公告)日：2018-08-14

申请号：US15521666

申请日：2016-10-11

Applicant: Boe Technology Group Co., Ltd. ,  Beijing Boe Display Technology Co., Ltd.

Inventor： Kan Zhang ,  Bin Zhang ,  Pengming Chen ,  Guangxing Wang ,  Qiang Zhang ,  Dianzheng Dong

IPC: G09G3/36

Abstract: The disclosure provides a pixel circuit and a driving method thereof, a driving circuit, and a display device, which pertains to the field of pixel driving technology. The pixel circuit includes a capacitor, a capacitor charging transistor, a first and second capacitor discharging transistor. The capacitor is charged to a first voltage greater than the pixel voltage when the capacitor charging transistor is turned on. The capacitor is connected in series with the first and second capacitor discharging transistor to form a discharge circuit, and the capacitor is discharged when the first and second capacitor discharging transistor are turned on so that the voltage across the capacitor drops from the first voltage to the pixel voltage. There is no need to arrange a Gamma resistor for the driving circuit for the pixel circuit array provided by the disclosure, which makes the structure simple and the power consumption in driving low.

公开(公告)号：US20180019346A1

公开(公告)日：2018-01-18

申请号：US15718778

申请日：2017-09-28

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Jincheng GAO ,  Bin Zhang ,  Xiaolong He ,  Xiangchun Kong ,  Qi Yao ,  Zhanfeng Cao ,  Zhengliang Li

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/45 ,  H01L27/12

CPC classification number: H01L29/78606 ,  H01L27/1225 ,  H01L27/127 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696

Abstract: A thin film transistor, a method of fabricating the same, an array substrate and a display device are disclosed. The method of fabricating the thin film transistor comprises: forming a semiconductor layer; forming a conductive film that does not react with acid solution on the semiconductor layer to be employed as a protective layer; forming a source electrode and a drain electrode on the protective layer; and removing a portion of the protective layer between the source electrode and the drain electrode to expose a portion of the semiconductor layer between the source electrode and the drain electrode.

公开(公告)号：US20170365684A1

公开(公告)日：2017-12-21

申请号：US15519324

申请日：2016-09-01

Applicant: BOE Technology Group Co., Ltd.

Inventor： Bin Zhang ,  Tingting Zhou ,  Zhen Liu ,  Zhanfeng Cao ,  Shi Shu ,  Qi Yao ,  Feng Guan

IPC: H01L29/66 ,  H01L27/12 ,  H01L21/027 ,  G03F7/40 ,  G03F7/20 ,  H01L29/786 ,  G03F7/16

CPC classification number: H01L29/6675 ,  G03F7/094 ,  G03F7/16 ,  G03F7/20 ,  G03F7/201 ,  G03F7/2022 ,  G03F7/2026 ,  G03F7/203 ,  G03F7/40 ,  H01L21/027 ,  H01L21/0274 ,  H01L27/12 ,  H01L29/78621 ,  H01L29/7869

Abstract: A method for forming a mask pattern is provided, comprising forming a negative photoresist on a substrate; in an environment without oxygen, to performing a first exposure on the negative photoresist by use of a first ordinary mask plate, so that a fully-cured portion of the negative photoresist is exposed to light and a semi-cured portion and a removed portion of the negative photoresist are not exposed to light; in an environment with oxygen, performing a second exposure on the negative photoresist by use of a second ordinary mask plate, so that the semi-cured portion of the negative photoresist is exposed to light and the removed portion of the negative photoresist not exposed to light; removing the uncured negative photoresist and forming the mask pattern.

公开(公告)号：US09812469B2

公开(公告)日：2017-11-07

申请号：US15150549

申请日：2016-05-10

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zhanfeng Cao ,  Feng Zhang ,  Bin Zhang ,  Xiaolong He ,  Jincheng Gao ,  Qi Yao ,  Zhengliang Li ,  Xiangchun Kong

IPC: H01L27/12 ,  H01L29/423 ,  H01L29/417

CPC classification number: H01L27/124 ,  H01L29/41733 ,  H01L29/42384

Abstract: An array substrate and a display device are disclosed. The array substrate includes a peripheral area in which a plurality of gate electrode material lines, a plurality of source-drain electrode material lines and a plurality of first metal lines are disposed. Overlapping areas are provided between or among the gate electrode material lines, the source-drain material lines and the first metal lines; a number of the overlapping areas of the source-drain material lines and the first metal lines is less than a number of the overlapping areas of the source-drain material lines and the gate electrode material lines; the gate electrode material lines, the source-drain material lines and the first metal lines are configured as connecting lines of circuits in the peripheral area.

公开(公告)号：US20170098714A1

公开(公告)日：2017-04-06

申请号：US14905251

申请日：2015-08-05

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zhengliang Li ,  Qi Yao ,  Zhanfeng Cao ,  Bin Zhang ,  Xiaolong He ,  Jincheng Gao ,  Xiangchun Kong ,  Wei Zhang

IPC: H01L29/786 ,  H01L21/28 ,  H01L29/49 ,  H01L27/12 ,  H01L29/45

CPC classification number: H01L29/78606 ,  H01L21/28 ,  H01L27/1262 ,  H01L29/45 ,  H01L29/4908

Abstract: Embodiments of the present invention disclose a thin film transistor and a manufacturing method thereof, an array substrate, and a display device, which relates to the field of display technology, and solves the problem that the adhesion of the electrode thin film with the adjacent thin film layer in the thin film transistor of the prior art is relatively bad. More specifically, an embodiment of the present invention provides a thin film transistor, comprising a gate, a source, a drain and a buffer layer, the buffer layer is located at one side or two sides of the gate, the source or the drain, the material of the buffer layer is a copper alloy material, the copper alloy material contains nitrogen element or oxygen element, the copper alloy material further contains aluminum element.

公开(公告)号：US20170052418A1

公开(公告)日：2017-02-23

申请号：US15138788

申请日：2016-04-26

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Bin Zhang ,  Shi SHU ,  Seong Yeol YOO ,  Tingting ZHOU ,  Zhanfeng CAO

IPC: G02F1/1362 ,  G02F1/1333 ,  G02F1/1368 ,  G02F1/1343 ,  H01L27/12 ,  H01L29/786

Abstract: An array substrate, a manufacturing method thereof, a liquid crystal display panel and a display device are provided. The array substrate includes a base substrate, an active layer, a gate insulating layer and a gate electrode which are located on the base substrate; a first insulating layer, a source electrode, a second insulating layer and a pixel electrode which are stacked on the active layer, the gate insulating layer and the gate electrode, sequentially; and a first connecting part and a second connecting part arranged on a same layer with the pixel electrode; wherein, the first connecting part is electrically connected with the active layer and the source electrode, and the second connecting part is electrically connected with the active layer and the pixel electrode.

Abstract translation: 提供阵列基板，其制造方法，液晶显示面板和显示装置。 阵列基板包括位于基底基板上的基底基板，有源层，栅极绝缘层和栅极电极; 顺序地层叠在有源层，栅极绝缘层和栅电极上的第一绝缘层，源电极，第二绝缘层和像素电极; 以及与所述像素电极配置在同一层上的第一连接部和第二连接部; 其中，所述第一连接部与所述有源层和所述源电极电连接，所述第二连接部与所述有源层和所述像素电极电连接。