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    NON-VOLATILE MEMORY INCLUDING SELECTIVE ERROR CORRECTION
    93.
    发明申请
    NON-VOLATILE MEMORY INCLUDING SELECTIVE ERROR CORRECTION 审中-公开

    公开(公告)号：US20170206131A1

    公开(公告)日：2017-07-20

    申请号：US14997164

    申请日：2016-01-15

    Applicant: Micron Technology, Inc.

    Inventor： Carla L. Christensen

    IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52

    CPC classification number: G06F11/1072 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0688 ,  G11C2029/0411

    Abstract: Some embodiments include apparatuses and methods using a first memory area and a second memory area included a memory device, and using control circuitry included in the memory device to communicate with a memory controller. The memory controller includes an error correction engine. The control circuitry of the memory device is configured to retrieve the first information from the first memory area and store in the first information after the error correction engine performs an error detection operation on the first information. The control circuitry is configured to retrieve second information from the first memory area and store the second information in the second memory area without an additional error detection operation performed on the second information if a result from the error detection operation performed by the error correction engine on the first information meets a threshold condition.

    Memory chip, memory device, and reading method
    96.
    发明授权
    Memory chip, memory device, and reading method 有权

    公开(公告)号：US09685236B2

    公开(公告)日：2017-06-20

    申请号：US15398955

    申请日：2017-01-05

    Applicant: KABUSHIKI KAISHA TOSHIBA

    Inventor： Hiroyuki Nagashima

    IPC: G11C16/28 ,  G11C16/26 ,  G11C29/04

    CPC classification number: G11C16/26 ,  G06F11/08 ,  G11C16/0483 ,  G11C16/28 ,  G11C29/42 ,  G11C29/52 ,  G11C2029/0411

    Abstract: A memory chip includes a memory cell array having a plurality of memory cells connected to word lines and bit lines, and a sense amplifier configured to detect data stored in a memory cell that is connected to a selected one of the word lines and a selected one of the bit lines, and a control circuit configured to read data from the memory cell in a first read mode when a first command is received and in a second read mode when a second command is received. A peak or an average value of an operation current that is flowing between power supply and ground terminals of the memory chip during a read operation in the first read mode is less than a peak or an average value of the operation current during a read operation in the second read mode.

    DATA STORAGE DEVICE AND OPERATING METHOD THEREOF
    99.
    发明申请
    DATA STORAGE DEVICE AND OPERATING METHOD THEREOF 审中-公开

    公开(公告)号：US20170154657A1

    公开(公告)日：2017-06-01

    申请号：US15159421

    申请日：2016-05-19

    Applicant: SK hynix Inc.

    Inventor： Sang Gon KIM

    IPC: G11C7/00 ,  G11C29/52 ,  G06F11/10

    CPC classification number: G11C29/52 ,  G06F11/10 ,  G06F11/1048 ,  G06F11/1068 ,  G11C7/00 ,  G11C11/5642 ,  G11C2029/0411

    Abstract: A data storage device includes a memory device including memory regions classified into a plurality of memory groups each corresponding to a plurality read bias voltage groups; and a controller suitable for: performing for a target memory region a read retry operation based on a first read bias voltage group corresponding to a memory group in which the target memory region is included, and performing an additional read retry operation based on at least one of remaining read bias voltage groups excluding the first read bias voltage group among the plurality of read bias voltage groups, according to a result of the read retry operation.

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