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512 条记录 (耗时 0.027 秒)

    DATA TRANSMISSION APPARATUS AND DATA TRANSMISSION METHOD
    91.
    发明公开
    DATA TRANSMISSION APPARATUS AND DATA TRANSMISSION METHOD 审中-公开

    公开(公告)号：US20240012784A1

    公开(公告)日：2024-01-11

    申请号：US18471921

    申请日：2023-09-21

    申请人： Huawei Technologies Co., Ltd.

    发明人： Deng Lu ,  Zhaohua Qian ,  Weixing Zhang ,  Jiandong Ke

    IPC分类号： G06F13/42 ,  G06F13/40

    CPC分类号： G06F13/4282 ,  G06F13/40 ,  G06F2213/0042

    摘要： This application provides a data transmission apparatus and a data transmission method. The data transmission apparatus in this application includes: a first connection unit and a control unit, where the first connection unit is a connector plug or a connector socket; and the control unit is configured to: if determining that the first connection unit is in a forward insertion state, control a first data pin pair of the first connection unit to be in a first communication mode, and control a second data pin pair of the first connection unit to be in a second communication mode.

    Serial communications module with CRC
    92.
    发明授权
    Serial communications module with CRC 有权

    公开(公告)号：US11855655B2

    公开(公告)日：2023-12-26

    申请号：US17710906

    申请日：2022-03-31

    申请人： Texas Instruments Incorporated

    发明人： Robin Osa Hoel ,  Anand Kumar G ,  Dhivya Ravichandran ,  Aniruddha Periyapatna Nagendra

    IPC分类号： H03M13/09 ,  H03M13/00 ,  G06F13/40

    CPC分类号： H03M13/091 ,  G06F13/40 ,  H03M13/611

    摘要： A circuit with an interface, a transmit data register coupled to the interface, a storage device coupled to the transmit data register and including a plurality of storage locations, each storage location adapted to store a data unit, and a serial register coupled between the storage device and an output. The circuit also includes a CRC generation circuit having an input coupled between an output of the transmit data register and the storage device. The CRC generation circuit includes a first CRC generation block for providing a CRC in response to an X-bit data unit and an X-bit polynomial and a second CRC generation block with a collective X-bit input for providing a CRC in response to an X-bit data unit and a 2X-bit polynomial in a single clock cycle and a 2X-bit data unit and a 2X-bit polynomial in two clock cycles.

    VALID LANE TRAINING
    93.
    发明申请
    VALID LANE TRAINING 审中-公开

    公开(公告)号：US20190238179A1

    公开(公告)日：2019-08-01

    申请号：US15761408

    申请日：2015-09-26

    申请人： Intel Corporation

    发明人： Venkatraman Iyer ,  Lip Khoon Teh ,  Mahesh Wagh ,  Zuoguo Wu ,  Azydee Hamid ,  Gerald S. Pasdast

    IPC分类号： H04B3/40 ,  H04L25/03 ,  G06F13/20

    CPC分类号： H04B3/40 ,  G06F13/20 ,  G06F13/40 ,  H04L25/03006 ,  H04L2025/0377

    摘要： One or more link training signals are received, including instances of a link training pattern, on a plurality of lanes of a physical link that includes at least one valid lane and a plurality of data lanes. The plurality of lanes are trained together using the link training signals to synchronize sampling of the valid lane with sampling of the plurality of data lanes. An active link state is entered and a valid signal received on the valid lane during the active link state. The valid signal includes a signal held at a value for a defined first duration and indicates that data is to be received on the plurality of data lanes in a second defined duration subsequent to the first duration. The data is to be received, during the active link state, on the plurality of data lanes during the second defined duration.

    FPGA-based Interface Signal Remapping Method
    96.
    发明申请
    FPGA-based Interface Signal Remapping Method 审中-公开

    公开(公告)号：US20180107622A1

    公开(公告)日：2018-04-19

    申请号：US15565870

    申请日：2016-01-04

    申请人： State Nuclear Power Automation System Engineering Co., Ltd.

    发明人： JIAN ZHANG ,  QUNXING JIANG ,  XIAOKAI WANG

    IPC分类号： G06F13/42 ,  G06F1/24 ,  G06F1/12 ,  G06F5/14

    CPC分类号： G06F13/4239 ,  G06F1/12 ,  G06F1/24 ,  G06F5/14 ,  G06F13/40 ,  G06F2205/126

    摘要： An FPGA-based interface signal remapping method, relates to the technical field of nuclear power system, and solves the technical problems of poor reliability, readability and debuggability in the prior art. The method comprises dividing an internal programmable logic of an FPGA chip into two independent modules, with one module being an I/O module and the other module being a Core module, using the I/O module to process signal excursion occurring when an external signal is input to or output from the FPGA chip, signal collision caused by line multiplexing, metastable state in a data transmission process, and a data transmission error between asynchronous clock domains, using the Core module to implement logical processing and computing; and introducing a master clock signal outside the FPGA chip into the FPGA chip through a global clock pin of the FPGA chip. The method provided in the invention is suitable for a nuclear power protection system platform.

    Registered FIFO
    97.
    发明授权
    Registered FIFO 有权

    公开(公告)号：US09940097B1

    公开(公告)日：2018-04-10

    申请号：US14527550

    申请日：2014-10-29

    申请人： Netronome Systems, Inc.

    发明人： Ronald N. Fortino ,  Gavin J. Stark ,  Steven W. Zagorianakos

    IPC分类号： G06F3/00 ,  G06F5/00 ,  G06F5/14 ,  H04L25/00 ,  G06F13/40 ,  G06F9/34 ,  H04B1/38

    CPC分类号： G06F5/14 ,  G06F5/08 ,  G06F9/34 ,  G06F13/40 ,  G06F2205/126 ,  H04B1/38 ,  H04L25/00

    摘要： A registered synchronous FIFO has a tail register, internal registers, and a head register. The FIFO cannot be pushed if it is full and cannot be popped if it is empty, but otherwise can be pushed and/or popped. Within the FIFO, the internal signal fanout of incoming data circuitry and push control circuitry and is minimized and remains essentially constant regardless of the number of registers of the FIFO. The output delay of the output data also is essentially constant regardless of the number of registers of the FIFO. An incoming data value can only be written into the head or tail. If a data value is in the tail and one of the internal registers is empty, and if no push or pop is to be performed in a clock cycle, then nevertheless the data value in the tail is moved into the empty internal register in the cycle.