公开(公告)号：US12126381B2

公开(公告)日：2024-10-22

申请号：US17894966

申请日：2022-08-24

Applicant: MACOM Technology Solutions Holdings, Inc.

Inventor： Ryan Latchman

IPC: H04B10/2543 ,  H04B10/077 ,  H04B10/2507

CPC classification number: H04B10/2543 ,  H04B10/0775 ,  H04B10/25073

Abstract: A communication interface comprising a host with non-linear equalizers configured to perform non-linear equalization. Also part of the interface is a host to optic module channel electrically connecting the host to an optic module and the optic module. The optic module comprises a transmitter and a receiver. The transmitter includes a linear equalizer and an electrical to optical module configured to convert the equalized signal from the driver to an optical signal, and transmit the optical signal over a fiber optic cable, such that the transmitter does not perform non-linear processing. The receiver includes a photodetector, configured to convert the received optic signal to a received electrical signal, and a linear amplifier configured to perform linear amplification on the received electrical signal. A driver sends the amplified received signal over an optic module to host channel, such that the receive does not perform non-linear processing.

公开(公告)号：US12113538B2

公开(公告)日：2024-10-08

申请号：US17027539

申请日：2020-09-21

Applicant: MACOM Technology Solutions Holdings, Inc.

Inventor： Naga Rajesh Doppalapudi ,  Echere Iroaga

IPC: H04B17/15 ,  H03K5/05 ,  H03K5/135 ,  H03K5/156 ,  H03K5/00

CPC classification number: H03K5/1565 ,  H03K5/05 ,  H03K5/135 ,  H04B17/15 ,  H03K2005/00286

Abstract: Various aspects provide for error detection and compensation for a multiplexing transmitter. For example, a system can include an error detector circuit and a duty cycle correction circuit. The error detector circuit is configured to measure duty cycle error for a clock associated with a transmitter to generate error detector output based on a clock pattern for output generated by the transmitter in response to a defined bit pattern. The duty cycle correction circuit is configured to adjust the clock associated with the transmitter based on the error detector output. Additionally or alternatively, the error detector circuit is configured to measure quadrature error between an in-phase clock and a quadrature clock in response to the defined bit pattern. Additionally or alternatively, the system can include a quadrature error correction circuit configured to adjust phase shift between the in-phase clock and the quadrature clock based on quadrature error.

公开(公告)号：US12113490B2

公开(公告)日：2024-10-08

申请号：US18517065

申请日：2023-11-22

Applicant: MACOM Technology Solutions Holdings, Inc.

Inventor： Basim Noori ,  Marvin Marbell ,  Qianli Mu ,  Kwangmo Chris Lim ,  Michael E. Watts ,  Mario Bokatius ,  Jangheon Kim

IPC: H03F3/187 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L29/778 ,  H03F1/56 ,  H03F3/193

CPC classification number: H03F1/565 ,  H01L23/481 ,  H01L23/49822 ,  H01L24/08 ,  H01L29/778 ,  H03F3/193 ,  H01L2224/08225 ,  H03F2200/222 ,  H03F2200/387 ,  H03F2200/451

Abstract: RF transistor amplifiers include a Group III nitride-based RF transistor amplifier die that includes a semiconductor layer structure, a conductive source via that is connected to a source region of the Group III nitride-based RF transistor amplifier die, the conductive source via extending through the semiconductor layer structure, and an additional conductive via that extends through the semiconductor layer structure. A first end of the additional conductive via is connected to a first external circuit and a second end of the additional conductive via that is opposite the first end is connected to a first matching circuit.

公开(公告)号：US12112983B2

公开(公告)日：2024-10-08

申请号：US17003616

申请日：2020-08-26

Applicant: MACOM Technology Solutions Holdings, Inc.

Inventor： Timothy E. Boles ,  Wayne Mack Struble ,  Gabriel R. Cueva

IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/532 ,  H01L29/20 ,  H01L29/423

CPC classification number: H01L21/76841 ,  H01L21/823437 ,  H01L23/53223 ,  H01L29/2003 ,  H01L29/42372

Abstract: An electrode structure for a device, such as a GaN or AlGaN device is described. In one example, a method to form the structure includes providing a substrate including gallium nitride material, forming an insulating layer over a surface of the substrate, forming an opening in the insulating layer to expose a surface region of the substrate, depositing a barrier metal layer over the insulating layer and onto the surface region of the substrate through the opening, and depositing a conducting metal layer over the barrier metal layer. In one case, the barrier metal layer includes a layer of tungsten nitride. The layer of tungsten nitride is deposited over the insulating layer and onto the surface region of the substrate using atomic layer deposition.

公开(公告)号：US12080660B2

公开(公告)日：2024-09-03

申请号：US17228978

申请日：2021-04-13

Applicant: CREE, INC.

Inventor： Xikun Zhang ,  Dejiang Chang ,  Bill Agar ,  Michael Lefevre ,  Alexander Komposch

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/495 ,  H01L23/498 ,  H01L25/00 ,  H01L25/07 ,  H01L29/16

CPC classification number: H01L23/66 ,  H01L23/49503 ,  H01L23/49568 ,  H01L23/49575 ,  H01L23/49844 ,  H01L24/27 ,  H01L24/32 ,  H01L24/83 ,  H01L24/95 ,  H01L25/072 ,  H01L25/50 ,  H01L29/16 ,  H01L23/49534 ,  H01L23/49537 ,  H01L23/49582 ,  H01L23/49586 ,  H01L24/29 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L2223/6644 ,  H01L2223/6672 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83121 ,  H01L2224/83136 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/8384 ,  H01L2224/83855 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/8384 ,  H01L2924/00014 ,  H01L2224/83801 ,  H01L2924/00014 ,  H01L2224/2919 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2224/29101 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/29144 ,  H01L2924/0105 ,  H01L2224/29139 ,  H01L2924/0105 ,  H01L2224/29147 ,  H01L2924/0105 ,  H01L2224/83855 ,  H01L2924/00014 ,  H01L2224/73265 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2924/00012 ,  H01L2224/92247 ,  H01L2224/73265 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2924/00012

Abstract: A multi-die package includes a thermally conductive flange, a first semiconductor die made of a first semiconductor material attached to the thermally conductive flange via a first die attach material, a second semiconductor die attached to the same thermally conductive flange as the first semiconductor die via a second die attach material, and leads attached to the thermally conductive flange or to an insulating member secured to the flange. The leads are configured to provide external electrical access to the first and second semiconductor dies. The second semiconductor die is made of a second semiconductor material different than the first semiconductor material. Additional multi-die package embodiments are described.

公开(公告)号：US12046794B2

公开(公告)日：2024-07-23

申请号：US17673839

申请日：2022-02-17

Applicant: MACOM Technology Solutions Holdings, Inc.

Inventor： Michael O'Connor ,  Jean-Marc Mourant

IPC: H01P5/10 ,  H01P3/08 ,  H03H7/42

CPC classification number: H01P5/10 ,  H01P3/081 ,  H03H7/42 ,  H03H7/422

Abstract: A balun is enhanced with design features that extend the operational bandwidth of the balun allowing the balun to operate at lower frequencies. The design enhancements also suppress resonances that otherwise cause sudden power drops at a resonance frequency while a load is connected between the balun's differential outputs.

公开(公告)号：US12028025B2

公开(公告)日：2024-07-02

申请号：US17397833

申请日：2021-08-09

Applicant: MACOM Technology Solutions Holdings, Inc.

Inventor： John R. Francis

IPC: H03F3/45 ,  H03F1/30 ,  H03G3/30

CPC classification number: H03F1/30 ,  H03F3/45475 ,  H03G3/30 ,  H03F3/45484 ,  H03F2200/447 ,  H03G2201/103

Abstract: An amplifier with temperature compensation where the amplifier has transistors configured to amplify a received signal to create an amplified signal. The amplifier gain changes over temperature. A gain control circuit, connected to the amplifier, that adjusts the amplifier gain responsive to a gain control signal. A temperature compensation circuit includes numerous elements. A constant current source that generates a constant current which is used to create a constant voltage. A temperature dependent current source that generates a temperature dependent current which is used to create a temperature dependent voltage, such that the temperature dependent current source has an inverse temperature dependance as compared to the amplifier. An operational amplifier compares the constant voltage to the temperature dependent voltage and generates an offset signal which varies over temperature. A gated buffer is configured to receive the offset signal and responsive thereto, selectively modify the gain control signal.

公开(公告)号：US12021543B2

公开(公告)日：2024-06-25

申请号：US17836722

申请日：2022-06-09

Applicant: MACOM Technology Solution Holdings, Inc.

Inventor： David Foley

IPC: H03M1/12 ,  H03M1/00 ,  H03M1/10

CPC classification number: H03M1/1076 ,  H03M1/004 ,  H03M1/1095

Abstract: A baseline wander and offset correction system having inputs configured to receive input signals to be transmitted. Also part of the system is a driver circuit configured to receive and amplify the input signals. The driver circuit is configured with one or more transistors having an optional back bias terminal. A replica circuit receives the input signals and responsive thereto, generates back bias signals which are provided to the back bias terminal of the one or more transistors to change the back bias in response to the input signals having consecutive one values or consecutive zero values. This reduces the size of the one or more AC coupling capacitors located between the driver circuit and a channel. An embodiment may store back bias values in a memory. The back bias values are processed by DAC to generate the back bias signals for offset correction.

公开(公告)号：US12009788B2

公开(公告)日：2024-06-11

申请号：US16367631

申请日：2019-03-28

Applicant: MACOM Technology Solutions Holdings, Inc.

Inventor： Zulhazmi A. Mokhti ,  Frank Trang ,  Haedong Jang

IPC: H03F1/02 ,  H03F1/56 ,  H03F3/193 ,  H03F3/24

CPC classification number: H03F1/0288 ,  H03F1/0277 ,  H03F1/56 ,  H03F3/193 ,  H03F3/245

Abstract: A power amplifier includes a semiconductor die having a main amplifier and a peaking amplifier. The main amplifier includes at least one first transistor, and the peaking amplifier includes at least one second transistor that is different than the first transistor. The peaking amplifier is configured to modulate a load impedance of the main amplifier responsive to a common gate bias applied to respective gates of the first and second transistors. Related fabrication and methods of operation are also discussed.

公开(公告)号：US12009286B2

公开(公告)日：2024-06-11

申请号：US17504284

申请日：2021-10-18

Applicant: MACOM Technology Solutions Holdings, Inc.

Inventor： Soon Lee Liew ,  Eng Wah Woo ,  Alexander Komposch

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L23/49541 ,  H01L23/3178 ,  H01L23/481

Abstract: A method of forming a packaged semiconductor device according to some embodiments includes providing a leadframe blank including a first package blank, a second package blank and a tie bar between the first package blank and the second package blank, forming a recessed cavity in the tie bar, and separating the first and second package blanks by sawing through the leadframe blank along the tie bar.