Utilizing atomic layer deposition for programmable device
    91.
    发明申请
    Utilizing atomic layer deposition for programmable device 审中-公开
    利用原子层沉积可编程器件

    公开(公告)号:US20050124157A1

    公开(公告)日:2005-06-09

    申请号:US10971812

    申请日:2004-10-22

    摘要: In an aspect, an apparatus is provided that sets and reprograms the state of programmable devices. In an aspect, a method is provided such that an opening is formed through a dielectric exposing a contact, the contact formed on a substrate. An electrode is conformally deposited on a wall of the dielectric, utilizing atomic layer deposition (ALD). A programmable material is formed on the electrode and a conductor is formed to the programmable material. In an aspect, a barrier is conformally deposited utilizing ALD, between the electrode and the programmable material.

    摘要翻译: 在一方面,提供一种设置和重新编程可编程设备的状态的设备。 在一方面,提供了一种方法,使得通过暴露接触的电介质形成开口,接触形成在基底上。 利用原子层沉积(ALD)将电极保形地沉积在电介质的壁上。 可编程材料形成在电极上,导体形成可编程材料。 在一个方面,在电极和可编程材料之间利用ALD共形沉积屏障。

    Phase change material memory device
    93.
    发明申请
    Phase change material memory device 审中-公开
    相变材料存储器件

    公开(公告)号:US20050074933A1

    公开(公告)日:2005-04-07

    申请号:US10623861

    申请日:2003-07-21

    申请人: Tyler Lowrey

    发明人: Tyler Lowrey

    IPC分类号: H01L45/00 H01L21/8238

    摘要: A lower electrode may be covered by a protective film to reduce the exposure of the lower electrode to subsequent processing steps or the open environment. As a result, materials that may have advantageous properties as lower electrodes may be utilized despite the fact that they may be sensitive to subsequent processing steps or the open environment.

    摘要翻译: 下电极可以被保护膜覆盖,以减少下电极对后续处理步骤或开放环境的暴露。 结果,可以使用可能具有作为下电极的有利特性的材料,尽管它们可能对随后的加工步骤或开放环境敏感。

    Forming phase change memories
    94.
    发明授权
    Forming phase change memories 失效
    形成相变记忆

    公开(公告)号:US06869883B2

    公开(公告)日:2005-03-22

    申请号:US10319214

    申请日:2002-12-13

    IPC分类号: H01L45/00 H01L21/311

    摘要: Phase change memories may exhibit improved properties and lower cost in some cases by forming the phase change material layers in a planar configuration. A heater may be provided below the phase change material layers to appropriately heat the material to induce the phase changes. The heater may be coupled to an appropriate conductor.

    摘要翻译: 在一些情况下,通过将相变材料层形成为平面构型,相变存储器可以表现出改善的性能和较低的成本。 可以在相变材料层的下方设置加热器,以适当地加热材料以引起相变。 加热器可以耦合到适当的导体。

    Methods of fabricating buried digit lines and semiconductor devices including same
    95.
    发明申请
    Methods of fabricating buried digit lines and semiconductor devices including same 有权
    制造埋地数字线的方法及包括其的半导体器件

    公开(公告)号:US20050017281A1

    公开(公告)日:2005-01-27

    申请号:US10920938

    申请日:2004-08-17

    申请人: Tyler Lowrey

    发明人: Tyler Lowrey

    摘要: A method of electrically linking the contacts of a semiconductor device to their corresponding digit lines. The method includes disposing a quantity of mask material into a trench through which the contact is exposed. The mask also abuts a connect region of a conductive element of a corresponding digit line and, therefore, protrudes somewhat over a surface of the semiconductor device. A layer of insulative material is disposed over the semiconductor device with the mask material being exposed therethrough. The mask material is then removed, leaving open cavities that include the trench and a strap region continuous with the trench and with a connect region of the corresponding digit line. Conductive material is disposed within the cavity and electrically isolated from conductive material disposed in adjacent cavities, which define conductive plugs or studs and conductive straps from the conductive material. These plugs or studs and straps provide an electrically conductive link between each contact of the semiconductor device and its corresponding digit line. Semiconductor devices that include features that have been fabricated in accordance with the method of the present invention are also within the scope of the present invention.

    摘要翻译: 将半导体器件的触点电连接到其对应的数字线的方法。 该方法包括将一定量的掩模材料设置在暴露于触点的沟槽中。 掩模还邻接相应数字线的导电元件的连接区域,因此在半导体器件的表面上略微突出。 绝缘材料层设置在半导体器件上,掩模材料暴露在其中。 然后去除掩模材料,留下包括沟槽的开放空腔和与沟槽连续的带区域以及相应数字线的连接区域。 导电材料设置在空腔内并与设置在相邻空腔中的导电材料电绝缘,其从导电材料限定导电塞或螺栓和导电带。 这些插头或螺柱和带在半导体器件的每个触点与其对应的数字线之间提供导电连接。 包括根据本发明的方法制造的特征的半导体器件也在本发明的范围内。