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231 条记录 (耗时 0.023 秒)

    Hybrid MOSFET structure having drain side schottky junction
    94.
    发明授权
    Hybrid MOSFET structure having drain side schottky junction 有权
    具有漏极侧肖特基结的混合MOSFET结构

    公开(公告)号：US08610233B2

    公开(公告)日：2013-12-17

    申请号：US13049491

    申请日：2011-03-16

    申请人： Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

    发明人： Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

    IPC分类号： H01L31/102

    CPC分类号： H01L21/84 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/7839

    摘要： A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate, forming a raised source region over the semiconductor substrate adjacent a source side of the gate structure, and forming silicide contacts on the raised source region, on the patterned gate structure, and on the semiconductor substrate adjacent a drain side of the gate structure. Thereby, a hybrid field effect transistor (FET) structure having a drain side Schottky contact and a raised source side ohmic contact is defined.

    摘要翻译： 一种形成晶体管器件的方法包括在半导体衬底上形成图案化的栅极结构，在邻近栅极结构的源极侧的半导体衬底上形成凸起的源极区域，并在图案化的栅极上形成凸起的源极区域上的硅化物接触 并且在与栅极结构的漏极侧相邻的半导体衬底上。 因此，限定了具有漏极侧肖特基接触和升高的源极侧欧姆接触的混合场效应晶体管（FET）结构。

    Semiconductor structure having NFET and PFET formed in SOI substrate with underlapped extensions
    96.
    发明授权
    Semiconductor structure having NFET and PFET formed in SOI substrate with underlapped extensions 失效
    具有NFET和PFET的半导体结构形成在具有延伸延伸的SOI衬底中

    公开(公告)号：US08598663B2

    公开(公告)日：2013-12-03

    申请号：US13108290

    申请日：2011-05-16

    申请人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

    发明人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

    IPC分类号： H01L27/12 ,  H01L21/02 ,  H01L29/786 ,  H01L21/70

    CPC分类号： H01L27/1203 ,  H01L21/823864 ,  H01L21/823892

    摘要： A semiconductor structure which includes a semiconductor on insulator (SOI) substrate. The SOI substrate includes a base semiconductor layer; a buried oxide (BOX) layer in contact with the base semiconductor layer; and an SOI layer in contact with the BOX layer. The semiconductor structure further includes a circuit formed with respect to the SOI layer, the circuit including an N type field effect transistor (NFET) having source and drain extensions in the SOI layer and a gate; and a P type field effect transistor (PFET) having source and drain extensions in the SOI layer and a gate. There may also be a well under each of the NFET and PFET. There is a nonzero electrical bias being applied to the SOI substrate. One of the NFET extensions and PFET extensions may be underlapped with respect to the NFET gate or PFET gate, respectively.

    摘要翻译： 一种半导体结构，其包括绝缘体上半导体（SOI）基板。 SOI衬底包括基极半导体层; 与基底半导体层接触的掩埋氧化物（BOX）层; 以及与BOX层接触的SOI层。 半导体结构还包括相对于SOI层形成的电路，该电路包括在SOI层中具有源极和漏极延伸的N型场效应晶体管（NFET）和栅极; 以及在SOI层中具有源极和漏极延伸的P型场效应晶体管（PFET）和栅极。 每个NFET和PFET下面也可以有一个阱。 存在将非零电偏压施加到SOI衬底。 NFET扩展和PFET扩展中的一个可能分别相对于NFET栅极或PFET栅极被覆盖。

    Formation of embedded stressor through ion implantation
    99.
    发明授权
    Formation of embedded stressor through ion implantation 有权
    通过离子注入形成嵌入式应激源

    公开(公告)号：US08536032B2

    公开(公告)日：2013-09-17

    申请号：US13155878

    申请日：2011-06-08

    申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

    发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

    IPC分类号： H01L21/265

    CPC分类号： H01L29/66772 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/78654

    摘要： An extremely-thin silicon-on-insulator transistor includes a buried oxide layer above a substrate. The buried oxide layer, for example, has a thickness that is less than 50 nm. A silicon layer is above the buried oxide layer. A gate stack is on the silicon layer includes at least a gate dielectric formed on the silicon layer and a gate conductor formed on the gate dielectric. A gate spacer has a first part on the silicon layer and a second part adjacent to the gate stack. A first raised source/drain region and a second raised source/drain region each have a first part that includes a portion of the silicon layer and a second part adjacent to the gate spacer. At least one embedded stressor is formed at least partially within the substrate that imparts a predetermined stress on a silicon channel region formed within the silicon layer.

    摘要翻译： 极薄的绝缘体上硅晶体管包括在衬底上方的掩埋氧化物层。 掩埋氧化物层例如具有小于50nm的厚度。 硅层在掩埋氧化物层之上。 硅层上的栅极叠层包括至少形成在硅层上的栅极电介质和形成在栅极电介质上的栅极导体。 栅极间隔物在硅层上具有第一部分，第二部分邻近栅极堆叠。 第一升高的源极/漏极区域和第二升高的源极/漏极区域各自具有包括硅层的一部分的第一部分和与栅极间隔物相邻的第二部分。 至少部分地在衬底内形成至少一个嵌入式应力器，其在硅层中形成的硅沟道区域上施加预定的应力。